Jiwanjot Singh

12 papers Journal 10Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
A grid-compliant control approach for current reference generation strategy to improve Low-Voltage Ride-Through (LVRT) performance and power management in grid-tied PV system.
Comput. Electr. Eng.
Abhishek Kumar Singh, Dinesh Kumar Tiwari, Nalin Behari Dev Choudhury, Jiwanjot Singh
2025 J jnl
Image Visibility Patch-Aided Partial Discharge Recognition Framework for Identifying Defects in XLPE Cables.
IEEE Trans. Instrum. Meas.
Sayanjit Singha Roy, Ashish Paramane, Jiwanjot Singh, Soumya Chatterjee
2025 J jnl
Isolation Based Reduced Switch Nine-Level High-Gain Multilevel Inverter.
IEEE Trans. Ind. Electron.
Dinesh Kumar Tiwari, Abhishek Kumar Singh, Nalin Behari Dev Choudhury, Jiwanjot Singh
2024 J jnl
A modified modular multilevel converter to reduce the second order ripples in the submodule capacitor voltage: Design and analysis.
Int. J. Circuit Theory Appl.
Ramudu Ganji, Jiwanjot Singh
2024 J jnl
A multi-objective low-voltage ride-through control strategy for three-phase grid-interfaced solar power plant during symmetrical and asymmetrical faults
Int. J. Circuit Theory Appl.
Abhishek Kumar Singh, Dinesh Kumar Tiwari, Nalin Behari Dev Choudhury, Jiwanjot Singh
2024 J jnl
Isolation-based bidirectional generalized step-up multilevel converter with optimized device count.
Int. J. Circuit Theory Appl.
Dinesh Kumar Tiwari, Abhishek Kumar Singh, Nalin Behari Dev Choudhury, Jiwanjot Singh
2023 J jnl
Automated Space Charge Classification Inside ±500-kV HVDC Cable Insulation Using Fusion of Superpixel and Deep Features for Remote Condition Assessment.
IEEE Trans. Instrum. Meas.
Sayanjit Singha Roy, Ashish Paramane, Jiwanjot Singh, Arup Kumar Das, Soumya Chatterjee, Xiangrong Chen
2023 J jnl
Characterization and Identification of Electrical Tree Growth Stages Inside High-Voltage Cable Insulation.
IEEE Trans. Instrum. Meas.
Sayanjit Singha Roy, Ashish Paramane, Jiwanjot Singh, Soumya Chatterjee, Zelin Hong, Xiangrong Chen
2023 J jnl
High-gain nine-level switched-capacitor multilevel inverter featuring less number of devices and leakage current.
Int. J. Circuit Theory Appl.
Tamiru Debela Awas, Jiwanjot Singh
2022 J jnl
Evaluation of a grid-connected reduced-component boost multilevel inverter (BMLI) topology.
Int. J. Circuit Theory Appl.
Tamiru Debela, Jiwanjot Singh, Vijay K. Sood
2020 — conf
Improvement in Fault Clearance Time of the Cascaded H-Bridge Multilevel Inverter Using Novel Technique Based on Frequency Detection.
CoMSO
Hillol Phukan, Jiwanjot Singh
2020 — conf
Seven Level Enhanced Modified T-type Multilevel Inverter (MLI) with Reduce Part Count.
CoMSO
Hillol Phukan, Tamiru Debela, Jiwanjot Singh