Jiun-Lang Huang

79 papers A* 1A 10B 4C 2Misc 8Journal 19Unranked 35

Year	Rank	Type	Title / Venue / Authors
2024	B	`conf`	SARA: Semantic-assisted Reinforced Active Learning for Entity Alignment. IJCNN Ching-Hsuan Liu, Chih-Ming Chen, Jing-Kai Lou, Ming-Feng Tsai, Jiun-Lang Huang, Chuan-Ju Wang
2023	—	`conf`	BDD-Based Self-Test Program Generation for Processor Cores. ITC-Asia Hao Cheng, Chi-Jhe Li, Hung-Lin Chen, Jiun-Lang Huang
2022	—	`conf`	Intelligent Design Automation for Heterogeneous Integration. ISPD Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen
2022	—	`conf`	Test Response Compaction for Software-Based Self-Test. ITC-Asia Jia-Ruei Liang, Ya-Ni Hsieh, Jiun-Lang Huang
2021	—	`conf`	Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors. ITC-Asia Kai-Hsun Chen, Bo-Yi Yang, Jia-Ruei Liang, Hung-Lin Chen, Jiun-Lang Huang
2021	—	`conf`	Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen
2020	—	`conf`	DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator. ITC-Asia Kuen-Wei Yeh, Jiun-Lang Huang
2020	B	`conf`	Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model. ETS Ching-Yuan Chen, Ching-Hong Cheng, Jiun-Lang Huang, Krishnendu Chakrabarty
2020	A	`conf`	Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen
2019	—	`conf`	An FPGA-Based Data Receiver for Digital IC Testing. ITC-Asia Wei-Chen Huang, Guan-Hao Hou, Jiun-Lang Huang, Terry Kuo
2019	—	`conf`	Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test. ATS Ching-Yuan Chen, Jiun-Lang Huang
2019	C	`conf`	Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. DDECS Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang
2018	—	`conf`	A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction. ISOCC Bo-Yi Li, Jiun-Lang Huang
2018	J	`jnl`	Conference Reports: Report on 2017 IEEE Asian Test Symposium. IEEE Des. Test Jin-Fu Li, Jiun-Lang Huang
2018	—	`conf`	Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter. ATS Guan-Hao Hou, Wei-Chen Huang, Jiun-Lang Huang, Terry Kuo
2017	—	`conf`	Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation. ATS Yang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, Jiun-Lang Huang, Terry Kuo
2017	—	`conf`	Source code transformation for software-based on-line error detection. DSC Tsung-Yen Tsai, Jiun-Lang Huang
2016	—	`conf`	An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing. ATS Po-Fan Hou, Yi-Tsung Lin, Jiun-Lang Huang, Ann Shih, Zoe F. Conroy
2016	J	`jnl`	CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. J. Electron. Test. Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang
2015	—	`conf`	A test-application-count based learning technique for test time reduction. VLSI-DAT Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng
2015	J	`jnl`	Design and Implementation of an FPGA-Based Data/Timing Formatter. J. Electron. Test. Yu-Yi Chen, Jiun-Lang Huang, Terry Kuo, Xuan-Lun Huang
2015	J	`jnl`	Design, Automation, and Test for Low-Power and Reliable Flexible Electronics. Found. Trends Electron. Des. Autom. Tsung-Ching Jim Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
2015	—	`conf`	SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. ATS Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang
2014	—	`conf`	FPGA-Based Subset Sum Delay Lines. ATS Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang
2013	A	`conf`	A circular pipeline processing based deterministic parallel test pattern generator. ITC Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang
2013	B	`conf`	A mutual characterization based SAR ADC self-testing technique. ETS H.-J. Lin, Xuan-Lun Huang, Jiun-Lang Huang
2013	A	`conf`	An IDDQ-based source driver IC design-for-test technique. ICCAD S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang
2013	—	`conf`	Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. Asian Test Symposium Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning
2013	—	`conf`	Improve speed path identification with suspect path expressions. VLSI-DAT Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng
2013	J	`jnl`	Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. Very Large Scale Integr. Syst. Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu
2013	Misc	`conf`	On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang
2013	J	`jnl`	Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning
2012	—	`conf`	A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC. Asian Test Symposium Y.-H. Chou, Jiun-Lang Huang, Xuan-Lun Huang
2012	Misc	`conf`	A SAR ADC missing-decision level detection and removal technique. VTS Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai
2012	—	`conf`	A Transition Isolation Scan Cell Design for Low Shift and Capture Power. Asian Test Symposium Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen
2012	J	`jnl`	An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. J. Electron. Test. Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai
2012	J	`jnl`	Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
2011	B	`conf`	A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. ETS Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai
2011	J	`jnl`	A Promising Alternative to Conventional Silicon. IEEE Des. Test Comput. Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
2011	—	`conf`	A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
2011	J	`jnl`	ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling. IEEE Trans. Very Large Scale Integr. Syst. Xuan-Lun Huang, Jiun-Lang Huang
2011	A	`conf`	Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. ITC Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen
2011	J	`jnl`	Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs. J. Electron. Test. Xuan-Lun Huang, Ping-Ying Kang, Yuan-Chi Yu, Jiun-Lang Huang
2011	J	`jnl`	Robust Circuit Design for Flexible Electronics. IEEE Des. Test Comput. Tsung-Ching Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
2011	J	`jnl`	Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu
2010	A	`conf`	A robust ADC code hit counting technique. DATE Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang
2010	A	`conf`	A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli
2010	Misc	`conf`	An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. VTS Xuan-Lun Huang, Jiun-Lang Huang
2010	A*	`conf`	An error tolerance scheme for 3D CMOS imagers. DAC Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu
2010	Misc	`conf`	CSER: BISER-based concurrent soft-error resilience. VTS Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li
2010	—	`conf`	Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng
2010	—	`conf`	Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing. Asian Test Symposium Chun-Yong Liang, Meng-Fan Wu, Jiun-Lang Huang
2009	J	`jnl`	A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays. J. Comput. Chen-Wei Lin, Jiun-Lang Huang
2009	—	`conf`	An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. Asian Test Symposium Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang
2009	—	`conf`	Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. ASP-DAC Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang
2009	J	`jnl`	LPTest: a Flexible Low-Power Test Pattern Generator. J. Electron. Test. Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang
2009	J	`jnl`	Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
2008	Misc	`conf`	A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. VTS Chen-Wei Lin, Jiun-Lang Huang
2008	—	`conf`	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte
2008	—	`conf`	PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment. ATS Yi-Tsung Lin, Meng-Fan Wu, Jiun-Lang Huang
2008	A	`conf`	Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing. ITC Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
2008	—	`conf`	Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry. ATS Jui-Jer Huang, Chiuan-Che Li, Jiun-Lang Huang
2007	—	`conf`	An Efficient Peak Power Reduction Technique for Scan Testing. ATS Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang
2006	J	`jnl`	A Low-Cost Jitter Measurement Technique for BIST Applications. J. Electron. Test. Jiun-Lang Huang, Jui-Jer Huang, Yuan-Shuang Liu
2006	—	`conf`	A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter. ATS Jiun-Lang Huang
2006	—	`conf`	A routability constrained scan chain ordering technique for test power reduction. ASP-DAC Xuan-Lun Huang, Jiun-Lang Huang
2006	J	`jnl`	On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines. J. Electron. Test. Jiun-Lang Huang
2005	—	`conf`	Random Jitter Testing Using Low Tap-Count Delay Lines. Asian Test Symposium Jiun-Lang Huang
2004	C	`conf`	An Infrastructure IP for On-Chip Clock Jitter Measurement. ICCD Jui-Jer Huang, Jiun-Lang Huang
2003	—	`conf`	A Low-Cost Jitter Measurement Technique for BIST Applications. Asian Test Symposium Jui-Jer Huang, Jiun-Lang Huang
2003	J	`jnl`	Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. IEEE Trans. Circuits Syst. II Express Briefs Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu, Ding-Ming Kwai
2002	—	`conf`	On-chip Analog Response Extraction with 1-Bit ? - Modulators. Asian Test Symposium Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu
2001	Misc	`conf`	An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. VTS Jiun-Lang Huang, Kwang-Ting Cheng
2000	A	`conf`	A BIST Scheme for On-Chip ADC and DAC Testing. DATE Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
2000	—	`conf`	A sigma-delta modulation based BIST scheme for mixed-signal circuits. ASP-DAC Jiun-Lang Huang, Kwang-Ting Cheng
2000	Misc	`conf`	Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. VTS Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
2000	A	`conf`	Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. ITC Jiun-Lang Huang, Kwang-Ting Cheng
1999	Misc	`conf`	Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. VTS Jiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng
1997	A	`conf`	Analog Fault Diagnosis for Unpowered Circuit Boards. ITC Jiun-Lang Huang, Kwang-Ting Cheng