Jitendra Khare

21 papers A* 1A 9Misc 8Journal 1Unranked 2
YearRankTypeTitle / Venue / Authors
2006 A conf
Embedded Memory Field Returns - Trials and Tribulations.
ITC
Jitendra Khare, Amit B. Shah, Ashok Raman, Girish Rayas
2004 A conf
Memory Yield Improvement - SoC Design Perspective.
ITC
Jitendra Khare
2004 A conf
Test Strategies For a 40Gbps Framer SoC.
ITC
Hans T. Heineken, Jitendra Khare
2003 A conf
DFM - A Fabless Perspective.
ITC
Jitendra Khare
2001 Misc conf
Enabling Embedded Memory Diagnosis via Test Response Compression.
VTS
John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare
2001 A conf
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.
ITC
John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
2000 Misc conf
Cost Trade-Offs in System On Chip Designs.
VLSI Design
Jitendra Khare, Hans T. Heineken, Manuel d'Abreu
2000 Misc conf
Manufacturability and Testability Oriented Synthesis.
VLSI Design
Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken
2000 Misc conf
Maximizing Wafer Productivity Through Layout Optimization.
VLSI Design
Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, Manuel d'Abreu
2000 Misc conf
Test and Debug of Networking SoCs: A Case Study.
VTS
A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su
1998 A conf
Design-Manufacturing Interface: Part I - Vision.
DATE
Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
1998 A conf
Design-Manufacturing Interface: Part II - Applications.
DATE
Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
1998 — conf
Manufacturability analysis of standard cell libraries.
CICC
Hans T. Heineken, Jitendra Khare, Manuel d'Abreu
1997 A* conf
CAD at the Design-Manufacturing Interface.
DAC
Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
1996 A conf
Design for manufacturability in submicron domain.
ICCAD
Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag
1996 Misc conf
Fault characterization of standard cell libraries using inductive contamination.
VTS
Jitendra Khare, Wojciech Maly, Nathan Tiday
1995 A conf
Inductive Contamination Analysis (ICA) with SRAM Application.
ITC
Jitendra Khare, Wojciech Maly
1995 Misc conf
Testability-oriented channel routing.
VLSI Design
Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar
1993 J jnl
Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits.
IEEE J. Solid State Circuits
Jitendra Khare, Derek B. I. Feltham, Wojciech Maly
1993 Misc conf
Estimation of reject ratio in testing of combinatorial circuits.
VTS
Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly
1992 — conf
Design for testability view on placement and routing.
EURO-DAC
Derek B. I. Feltham, Jitendra Khare, Wojciech Maly