Jirí Bucek - RankMe

25 papers C 13Journal 6Unranked 6

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Simple Power Analysis of Polynomial Multiplication in HQC. ICISSP (2) Pavel Velek, Tomás Rabas, Jirí Bucek
2026	J	`jnl`	Simple Power Analysis of Polynomial Multiplication in HQC. CoRR Pavel Velek, Tomás Rabas, Jirí Bucek
2025	—	`conf`	Profiling Side-Channel Attack on HQC Polynomial Multiplication Using Machine Learning Methods. CASCADE Tomás Rabas, Jirí Bucek, Vincent Grosso, Karolína Zenknerová, Róbert Lórencz
2024	J	`jnl`	Single-Trace Side-Channel Attacks on NTRU Implementation. SN Comput. Sci. Tomás Rabas, Jirí Bucek, Róbert Lórencz
2023	C	`conf`	SPA Attack on NTRU Protected Implementation with Sparse Representation of Private Key. ICISSP Tomás Rabas, Jirí Bucek, Róbert Lórencz
2023	C	`conf`	Single-Trace Attack on NTRU Decryption with Machine Learning and Template Profiling. DSD Tomás Rabas, Jirí Bucek, Róbert Lórencz
2022	J	`jnl`	Three counter value based ROPUFs on FPGA and their properties. Microprocess. Microsystems Filip Kodýtek, Róbert Lórencz, Jirí Bucek
2022	C	`conf`	Verification of PUF-based IoT Protocols with AVISPA and Scyther. SECRYPT Tomás Rabas, Róbert Lórencz, Jirí Bucek
2020	C	`conf`	Comparison of three counter value based ROPUFs on FPGA. DSD Filip Kodýtek, Róbert Lórencz, Jirí Bucek
2020	C	`conf`	Lightweight Authentication and Secure Communication Suitable for IoT Devices. ICISSP Simona Buchovecká, Róbert Lórencz, Jirí Bucek, Filip Kodýtek
2020	—	`conf`	Symmetric and Asymmetric Schemes for Lightweight Secure Communication. ICISSP (Revised Selected Papers) Simona Buchovecká, Róbert Lórencz, Jirí Bucek, Filip Kodýtek
2019	C	`conf`	Side-Channel Attack on the A5/1 Stream Cipher. DSD Martin Jurecek, Jirí Bucek, Róbert Lórencz
2017	J	`jnl`	Design of a Residue Number System Based Linear System Solver in Hardware. J. Signal Process. Syst. Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2017	J	`jnl`	True random number generator based on ring oscillator PUF circuit. Microprocess. Microsystems Simona Buchovecká, Róbert Lórencz, Filip Kodýtek, Jirí Bucek
2016	J	`jnl`	Improved ring oscillator PUF on FPGA and its properties. Microprocess. Microsystems Filip Kodýtek, Róbert Lórencz, Jirí Bucek
2016	C	`conf`	Polynomial Based NUC Implemented on FPGA. DSD Martin Rozkovec, Jirí Bucek
2016	C	`conf`	Temperature Dependence of ROPUF on FPGA. DSD Filip Kodýtek, Róbert Lórencz, Jirí Bucek, Simona Buchovecká
2016	C	`conf`	True Random Number Generator Based on ROPUF Circuit. DSD Simona Buchovecká, Róbert Lórencz, Filip Kodýtek, Jirí Bucek
2014	—	`conf`	An ASIC linear congruence solver synthesized with three cell libraries. ICECS Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2014	—	`conf`	System on chip design of a linear system solver. ISSoC Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2013	C	`conf`	Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver. DSD Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2013	C	`conf`	Differential Power Analysis under Constrained Budget: Low Cost Education of Hackers. DSD Filip Stepánek, Jirí Bucek, Martin Novotný
2012	—	`conf`	Dedicated hardware implementation of a linear congruence solver in FPGA. ICECS Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2006	C	`conf`	Comparing Subtraction-Free and Traditional AMI. DDECS Jirí Bucek, Róbert Lórencz
2006	C	`ed.`	Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 DDECS Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek