Jiren Yuan

26 papers C 2Journal 9Unranked 15
YearRankTypeTitle / Venue / Authors
2007 C conf
A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 µm CMOS.
ISCAS
Cheng Chen, Jiren Yuan
2005 — conf
Design considerations of a floating-point ADC with embedded S/H.
ISCAS (6)
Johan Piper, Jiren Yuan
2005 J jnl
Performance analysis of general charge sampling.
IEEE Trans. Circuits Syst. II Express Briefs
Gang Xu, Jiren Yuan
2004 — conf
A CMOS 500 MS/S charge sampler.
Circuits, Signals, and Systems
Gang Xu, Jiren Yuan
2004 — conf
A programmable analog-to-digital converter.
ISCAS (1)
Gang Xu, Jiren Yuan
2003 J jnl
A 10-bit wide-band CMOS direct digital RF amplitude modulator.
IEEE J. Solid State Circuits
Yijun Zhou, Jiren Yuan
2003 — conf
A Differential Difference Comparator for multi-step A/D converters.
ISCAS (1)
Gang Xu, Jiren Yuan
2003 — conf
A highly integrated CMOS direct digital RF quadrature modulator.
ESSCIRC
Yijun Zhou, Jiren Yuan
2003 J jnl
An 8-bit 100-MHz CMOS linear interpolation DAC.
IEEE J. Solid State Circuits
Yijun Zhou, Jiren Yuan
2003 — conf
An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average.
ISCAS (1)
Lixin Yang, Jiren Yuan
2003 — conf
Performance analysis of general charge sampling.
ISCAS (1)
Gang Xu, Jiren Yuan
2002 — conf
A direct digital RF amplitude modulator.
ISCAS (1)
Yijun Zhou, Jiren Yuan
2002 — conf
A non-feedback multiphase clock generator.
ISCAS (4)
Lixin Yang, Yijun Zhou, Jiren Yuan
2001 — conf
An 8-Bit, 100-MHz low glitch interpolation DAC.
ISCAS (4)
Yijun Zhou, Jiren Yuan
2001 — conf
An embedded low power FIR filter.
ISCAS (4)
Gang Xu, Jiren Yuan
2001 — conf
Realization of a floating-point A/D converter.
ISCAS (1)
Johan Piper, Jiren Yuan
2000 C conf
Single input current-sensing differential logic (SCSDL).
ISCAS
Roland Strandberg, Jiren Yuan
1999 — conf
Floating-point analog-to-digital converter.
ICECS
Jiren Yuan, Johan Piper
1997 J jnl
New single-clock CMOS latches and flipflops with improved speed and power savings.
IEEE J. Solid State Circuits
Jiren Yuan, Christer Svensson
1994 J jnl
A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS.
IEEE J. Solid State Circuits
Jiren Yuan, Crister Svensson
1994 J jnl
A 3-level asynchronous protocol for a differential two-wire communication link.
IEEE J. Solid State Circuits
Crister Svensson, Jiren Yuan
1993 J jnl
A 700-MHz 24-b pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator.
IEEE J. Solid State Circuits
Fang Lu, Henry Samueli, Jiren Yuan, Christer Svensson
1993 — conf
System Level Policies for Fault Tolerance Issues in the FERMI Project.
DFT
A. Dell'Acqua, M. Hansen, Sami J. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, Aurore Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson
1993 — conf
Ultra high speed CMOS design.
VLSI
Christer Svensson, Jiren Yuan
1991 J jnl
Double-edge-triggered D-flip-flops for high-speed CMOS circuits.
IEEE J. Solid State Circuits
Morteza Afghahi, Jiren Yuan
1989 J jnl
High-speed CMOS circuit technique.
IEEE J. Solid State Circuits
Jiren Yuan, Christer Svensson