Jiong Luo - RankMe

23 papers A* 4A 7C 1Misc 2Journal 5Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	IMH-MOT: Interactive Multi-Hierarchical Image and Point Cloud Fusion for Multi-Object Tracking. IEEE Robotics Autom. Lett. Wenyuan Qin, Zhiyan Zhou, Jiong Luo, Chengwei Pan, Hao Xu, Xiwang Dong, Danwei Wang
2022	A*	`conf`	Improving LUT-based optimization for ASICs. DAC Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon
2021	A*	`conf`	LUT-Based Optimization For ASIC Design Flow. DAC Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2020	A*	`conf`	SAT-Sweeping Enhanced for Logic Synthesis. DAC Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2019	A	`conf`	Scalable Boolean Methods in a Modern Synthesis Flow. DATE Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2018	A	`conf`	Improvements to boolean resynthesis. DATE Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2018	—	`conf`	Integrated ESOP Refactoring for Industrial Designs. ICECS Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli
2017	A	`conf`	Enabling exact delay synthesis. ICCAD Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2017	A	`conf`	Logic optimization and synthesis: Trends and directions in industry. DATE Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Janet Olson
2017	—	`conf`	Multi-level logic benchmarks: An exactness study. ASP-DAC Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2007	J	`jnl`	Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiong Luo, Niraj K. Jha
2007	J	`jnl`	Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. Jiong Luo, Niraj K. Jha, Li-Shiuan Peh
2005	J	`jnl`	Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Le Yan, Jiong Luo, Niraj K. Jha
2004	J	`jnl`	Register binding-based RTL power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiong Luo, Lin Zhong, Yunsi Fei, Niraj K. Jha
2003	—	`conf`	A comprehensive high-level synthesis system for control-flow intensive behaviors. ACM Great Lakes Symposium on VLSI Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha
2003	A	`conf`	Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. ICCAD Le Yan, Jiong Luo, Niraj K. Jha
2003	Misc	`conf`	Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. VLSI Design Jiong Luo, Niraj K. Jha
2003	A	`conf`	Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. DATE Jiong Luo, Li-Shiuan Peh, Niraj K. Jha
2002	Misc	`conf`	Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. HiPC Jiong Luo, Niraj K. Jha
2002	C	`conf`	Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. ICCD Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha
2002	—	`conf`	Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. ASP-DAC/VLSI Design Jiong Luo, Niraj K. Jha
2001	A*	`conf`	Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. DAC Jiong Luo, Niraj K. Jha
2000	A	`conf`	Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. ICCAD Jiong Luo, Niraj K. Jha