Jinn-Shyan Wang

123 papers A* 2A 6C 12Journal 51Unranked 52
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Chien-Tung Liu, Yu-Chuan Hou
2024 — conf
A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing.
HCS
Tay-Jyi Lin, Ze Li, Yun-Cheng Chen, Chien-Tung Liu, Tien-Fu Chen, Jinn-Shyan Wang
2024 J jnl
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jinn-Shyan Wang, Pei-Yuan Chou
2024 J jnl
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency.
Integr.
Jinn-Shyan Wang, Yu-Hsuan Kuo
2024 — conf
In-Situ Critical-Path Replica for Variation-Aware Low-Power Designs with Timing Margin Detection.
APCCAS
Jinn-Shyan Wang, Yong-Chin Miu, Chia-Hua Wu
2023 J jnl
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN.
IEEE Trans. Circuits Syst. II Express Briefs
Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang
2022 — conf
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients.
ASP-DAC
Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang
2020 C conf
A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods.
ISCAS
Jinn-Shyan Wang, Cheng-Xin Xue, Chien-Tung Liu, Tay-Jyi Lin
2020 — conf
Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems.
VLSI-DAT
Jinn-Shyan Wang, Chien-Tung Liu, Chao-Hsiang Wang
2019 J jnl
An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pei-Yuan Chou, Jinn-Shyan Wang
2018 J jnl
A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yung-Chen Chien, Jinn-Shyan Wang
2018 — conf
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs.
SoCC
Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin
2018 — conf
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications.
SoCC
Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang
2017 — conf
An all-n-type dynamic adder for ultra-low-leakage IoT devices.
ASICON
Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang
2017 — conf
Approximate Distributed Arithmetic for Variable-Latency Table Lookup.
NGCAS
Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang
2017 J jnl
Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Jinn-Shyan Wang, Shih-Nung Wei
2017 J jnl
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
2016 J jnl
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors.
Integr.
Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
2016 — conf
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction.
ASP-DAC
Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang
2016 — conf
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation.
SoCC
Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang
2016 — conf
Variable-length VLIW encoding for code size reduction in embedded processors.
SoCC
Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen
2016 J jnl
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.
IEEE Trans. Circuits Syst. II Express Briefs
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
2015 J jnl
A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs.
IEEE Trans. Multi Scale Comput. Syst.
Jinn-Shyan Wang, Yung-Chen Chien, Fengzhi Liu, Pei-Yao Chang
2015 J jnl
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang
2015 J jnl
An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jinn-Shyan Wang, Chun-Yuan Cheng
2015 — conf
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches.
ASICON
Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang
2014 — conf
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm
A-SSCC
Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang
2014 — conf
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET).
Hot Chips Symposium
Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang
2013 — conf
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.
ISSCC
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
2013 J jnl
A high-throughput and high-capacity IPv6 routing lookup system.
Comput. Networks
Yi-Mao Hsiao, Yuan-Sun Chu, Jeng-Farn Lee, Jinn-Shyan Wang
2013 — conf
An energy-efficient truly all-digital temperature sensor for SoC applications.
ACM Great Lakes Symposium on VLSI
Tzu-Yuan Kuo, Keng-Jui Chang, Jen-Hsiang Lee, Zong-Wu He, Jinn-Shyan Wang
2013 J jnl
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections.
IEEE Trans. Very Large Scale Integr. Syst.
Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang
2013 — conf
Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS.
ISSCC
Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang
2013 C conf
Variation-aware and adaptive-latency accesses for reliable low voltage caches.
VLSI-SoC
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
2012 J jnl
A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Yen-Hsiang Yu
2012 J jnl
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security.
IEEE Trans. Very Large Scale Integr. Syst.
Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang
2012 J jnl
An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology.
J. Circuits Syst. Comput.
Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh
2012 J jnl
Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier.
IEICE Trans. Electron.
Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin
2012 — conf
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment.
VLSIC
Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu
2012 J jnl
Towards Process Variation-Aware Power Gating.
IEEE Trans. Very Large Scale Integr. Syst.
Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang
2011 — conf
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video.
ASP-DAC
Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng
2011 J jnl
A dynamic quality-adjustable H.264 intra coder.
IEEE Trans. Consumer Electron.
Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, Jiun-In Guo
2011 — conf
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs.
ASICON
Jinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang
2011 J jnl
Design of High-Performance CMOS Level Converters Considering PVT Variations.
IEICE Trans. Electron.
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh
2011 J jnl
Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, Jiun-In Guo
2011 — conf
Low power shift registers for megabits CMOS image sensors.
ASICON
Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh
2011 — conf
RSCE-aware ultra-low-voltage 40-nm CMOS circuits.
ISOCC
Jinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh
2011 — conf
Variation-resilient voltage generation for SRAM weak cell testing.
ASICON
Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang
2010 C conf
A 55nm 1GHz one-cycle-locking de-skewing circuit.
ISCAS
Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang
2010 J jnl
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang
2010 J jnl
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays.
IEICE Trans. Electron.
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh
2009 J jnl
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications.
IEEE Trans. Circuits Syst. Video Technol.
Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo
2009 C conf
A Dynamic Quality-scalable H.264 Video Encoder.
ISCAS
Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo
2009 — conf
A dynamic quality-scalable H.264 video encoder chip.
ASP-DAC
Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang
2009 J jnl
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices.
IEEE J. Solid State Circuits
Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang
2009 A* conf
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.
DAC
Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang
2009 J jnl
VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism.
IEEE Trans. Circuits Syst. Video Technol.
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, Jinn-Shyan Wang
2008 C conf
A low-voltage latch-adder based tree multiplier.
ISCAS
Tzu-Yuan Kuo, Jinn-Shyan Wang
2008 — conf
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices.
ISSCC
Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang
2008 J jnl
High-Speed and Low-Power Design Techniques for TCAM Macros.
IEEE J. Solid State Circuits
Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh
2007 J jnl
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications.
IEEE J. Solid State Circuits
Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang
2007 — conf
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS.
ISSCC
Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh
2007 — conf
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip.
ISSCC
Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo
2007 — conf
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons.
SiPS
Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo
2006 — conf
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.
DATE Designers' Forum
Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang
2006 A conf
A Condition-based Intra Prediction Algorithm for H.264/AVC.
ICME
Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang
2006 J jnl
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264.
IEEE Trans. Circuits Syst. Video Technol.
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
2006 C conf
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm.
ISCAS
Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo
2006 — conf
An 830mW, 586kbps 1024-bit RSA chip design.
DATE Designers' Forum
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
2006 J jnl
An AND-type match-line scheme for high-performance energy-efficient content addressable memories.
IEEE J. Solid State Circuits
Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh
2006 C conf
An improved SAR controller for DLL applications.
ISCAS
Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu
2006 C conf
Design of STR level converters for SoCs using the multi-island dual-VDD design technique.
ISCAS
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu
2006 — conf
Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application.
ICASSP (3)
Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang
2006 — conf
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines.
ISSCC
Jinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh
2005 — conf
A low-power high-SFDR CMOS direct digital frequency synthesizer.
ISCAS (2)
Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
2005 J jnl
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.
IEEE Trans. Circuits Syst. Video Technol.
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen
2005 — conf
An all-digital pulsewidth control loop.
ISCAS (2)
Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang
2005 — conf
An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264.
ISCAS (5)
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
2005 A conf
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design.
ISLPED
Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo
2005 J jnl
Design techniques for single-low-V
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen
2004 J jnl
A low-power half-delay-line fast skew-compensation circuit.
IEEE J. Solid State Circuits
Yi-Ming Wang, Jinn-Shyan Wang
2004 — conf
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.
ISCAS (2)
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen
2004 A conf
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding.
ICME
Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh
2004 — conf
A reliable low-power fast skew-compensation circuit.
ASP-DAC
Yi-Ming Wang, Jinn-Shyan Wang
2004 — conf
An all-digital 50% duty-cycle corrector.
ISCAS (2)
Yi-Ming Wang, Jinn-Shyan Wang
2004 A conf
Low-power fixed-width array multipliers.
ISLPED
Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang
2004 — conf
Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs.
ISCAS (2)
Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh
2004 J jnl
The CMOS carry-forward adders.
IEEE J. Solid State Circuits
Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang
2003 J jnl
Design theory and implementation for low-power segmented bus systems.
ACM Trans. Design Autom. Electr. Syst.
Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen
2003 J jnl
Energy Efficient Caching-on-Cache Architectures for Embedded Systems.
J. Inf. Sci. Eng.
Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang
2003 J jnl
High-performance and power-efficient CMOS comparators.
IEEE J. Solid State Circuits
Chung-Hsun Huang, Jinn-Shyan Wang
2002 J jnl
An Associative Architecture of CMAC for Mobile Robot Motion Control.
J. Inf. Sci. Eng.
Yuan-Pao Hsu, Kao-Shing Hwang, Jinn-Shyan Wang
2002 J jnl
Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques.
IEEE J. Solid State Circuits
Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang
2002 J jnl
Low-voltage pulsewidth control loops for SOC applications.
IEEE J. Solid State Circuits
Po-Hui Yang, Jinn-Shyan Wang
2001 — conf
A contention-alleviated static keeper for high-performance domino logic circuits.
ICECS
Shang-Jyh Shieh, Jinn-Shyan Wang, Yuan-Hsun Yeh
2001 — conf
A high-efficiency CMOS charge pump circuit.
ISCAS (4)
Sheng-Yeh Lai, Jinn-Shyan Wang
2001 — conf
A high-speed CMOS incrementer/decrementer.
ISCAS (4)
Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang
2001 J jnl
Analysis and design of high-speed and low-power CMOS PLAs.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh
2001 J jnl
Charge-sharing alleviation and detection for CMOS domino circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
2001 — conf
Design of low-power domino circuits using multiple supply voltages.
ICECS
Shang-Jyh Shieh, Jinn-Shyan Wang
2001 J jnl
Low-power and high-speed ROM modules for ASIC applications.
IEEE J. Solid State Circuits
Ching-Rong Chang, Jinn-Shyan Wang, Cheng-Hui Yang
2000 C conf
A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops.
ISCAS
Po-Hui Yang, Jinn-Shyan Wang, Yi-Ming Wang
2000 C conf
A compact adaptive equalizer IC for HIPERLAN system.
ISCAS
Jinn-Shyan Wang, Pei-Lung Lin, Wern-Ho Sheen, Duo Sheng, Yu-Ming Huang
2000 C conf
A high-speed single-phase-clocked CMOS priority encoder.
ISCAS
Jinn-Shyan Wang, Chun-Shing Huang
2000 — conf
A new CMAC neural network architecture and its ASIC realization.
ASP-DAC
Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang
2000 — conf
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits.
LATW
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
2000 — conf
Charge sharing fault analysis and testing for CMOS domino logic circuits.
Asian Test Symposium
Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
2000 J jnl
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng
2000 J jnl
High-speed and low-power CMOS priority encoders.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Chung-Hsun Huang
2000 — conf
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.
DFT
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
2000 J jnl
Low-power embedded SRAM with the current-mode write technique.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Wayne Tseng, Hung-Yu Li
2000 — conf
Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier.
ASP-DAC
Jinn-Shyan Wang, Po-Hui Yang
2000 A conf
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.
ICCAD
Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang
1999 — conf
A cell selection strategy for low power applications.
ISCAS (6)
Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang
1999 — conf
A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM.
ISCAS (1)
Ching-Rong Chang, Jinn-Shyan Wang
1999 — conf
Charge Sharing Fault Detection for CMOS Domino Logic Circuits.
DFT
Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
1999 A* conf
Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs.
DAC
Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang
1999 J jnl
Segmented bus design for low-power systems.
IEEE Trans. Very Large Scale Integr. Syst.
J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen
1999 — conf
Technnology Mapping for Low Power.
ASP-DAC
Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang
1998 A conf
Low-power embedded SRAM macros with current-mode read/write operations.
ISLPED
Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng
1995 C conf
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
ISCAS
Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu
1993 J jnl
Analysis and design of a new race-free four-phase CMOS logic.
IEEE J. Solid State Circuits
Chung-Yu Wu, Kuo-Hsing Cheng, Jinn-Shyan Wang
1989 J jnl
CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Chung-Yu Wu, Ming-Kai Tsai