Jinmei Lai - RankMe

72 papers A 10B 3C 1Misc 1Journal 19Unranked 38

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	An Efficient Traversal Method for FPGA Interconnect Testing Based on Regular Routing. FPGA Wenwei Chen, Lin Ye, Xiaotong Zhao, Tongshu Ding, Jian Wang, Jinmei Lai
2025	B	`conf`	EQViTA: an End-To-End Quantized Vision Transformer Accelerator Implemented on Resource-Constrained FPGAs. FPL Jiacheng Cao, Jiaqi Guo, Wei Xiong, Huanlin Luo, Jian Wang, Jinmei Lai
2025	J	`jnl`	Shrink eFPGA tile area by using custom cells and optimizing routing congestion. Microelectron. J. Yanze Li, Jian Wang, Jinmei Lai
2024	J	`jnl`	A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Wei Xiong, Jiacheng Cao, Yaozhang Liu, Jian Wang, Jinmei Lai, Miaoqing Huang
2024	J	`jnl`	An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain-computer interfaces. Microelectron. J. Jiacheng Cao, Wei Xiong, Jie Lu, Peilin Chen, Jian Wang, Jinmei Lai, Miaoqing Huang
2024	—	`conf`	Testing Method for Embedded UltraRAM in Field Programmable Gate Arrays. ATS Jiaqi Guo, Wei Xiong, Jian Wang, Jinmei Lai
2023	—	`conf`	A High-Performance YOLOV5 Accelerator for Object Detection with Near Sensor Intelligence. ASICON Jiacheng Cao, Ziyi Yang, Jie Lu, Jinmei Lai
2023	—	`conf`	An Accurate Area Model for FPGA Circuits at Advanced Technologies. ASICON Yanze Li, Zeyu Sun, Jianfan Zhang, Zhichao Wei, Jian Wang, Jinmei Lai
2023	J	`jnl`	EdgeMedNet: Lightweight and Accurate U-Net for Implementing Efficient Medical Image Segmentation on Edge Devices. IEEE Trans. Circuits Syst. II Express Briefs Qingliang Liu, Shuai Zhou, Jinmei Lai
2023	—	`conf`	Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. ASICON Honghong Long, Yu Bai, Yanze Li, Jian Wang, Jinmei Lai
2022	J	`jnl`	3-D Auxiliary Classifier GAN for Hyperspectral Anomaly Detection via Weakly Supervised Learning. IEEE Geosci. Remote. Sens. Lett. Huanlin Luo, Haowen Zhu, Shengyang Liu, Yichuan Liu, Xinzhong Zhu, Jinmei Lai
2022	—	`conf`	An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique. ACM Great Lakes Symposium on VLSI Wei Xiong, Yanze Li, Changpeng Sun, Huanlin Luo, Jiafeng Liu, Jian Wang, Jinmei Lai, Gang Qu
2022	J	`jnl`	An Efficient Channel-Aware Sparse Binarized Neural Networks Inference Accelerator. IEEE Trans. Circuits Syst. II Express Briefs Qingliang Liu, Jinmei Lai, Jiabao Gao
2022	J	`jnl`	AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design. Integr. Yanze Li, Yufan Zhang, Jiafeng Liu, Jun Gong, Jian Wang, Jinmei Lai, Xinxuan Tao, Gang Qu
2021	Misc	`conf`	AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design. FCCM Yanze Li, Yufan Zhang, Jiafeng Liu, Jian Wang, Jinmei Lai, Gang Qu
2021	J	`jnl`	FCA-BNN: Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA. IEICE Trans. Inf. Syst. Jiabao Gao, Yuchen Yao, Zhengjie Li, Jinmei Lai
2021	J	`jnl`	HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure. IEICE Trans. Inf. Syst. Zhengjie Li, Jiabao Gao, Jinmei Lai
2021	C	`conf`	TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference. ISCAS Qingliang Liu, Jiabao Gao, Jinmei Lai
2020	—	`conf`	A Tile-based Interconnect Model for FPGA Architecture Exploration. ACM Great Lakes Symposium on VLSI Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai
2020	A	`conf`	FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA. FPGA Yufan Zhang, Zhengjie Li, Jian Wang, Jinmei Lai
2020	—	`conf`	HRAE: Hardware-assisted Randomization against Adversarial Example Attacks. ATS Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang
2020	A	`conf`	INTB: A New FPGA Interconnect Model for Architecture Exploration. FPGA Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai
2019	—	`conf`	A Polymorphic Circuit Interoperability Framework. ASICON Timothy Dunlap, Gang Qu, Jinmei Lai
2019	—	`conf`	A Web-based Waveform Viewer for BR0101 Chip Testing Platform. ASICON Xinyu He, Xie Xie, Jinmei Lai, Jian Wang
2019	—	`conf`	An Analytical-based Hybrid Algorithm for FPGA Placement. ACM Great Lakes Symposium on VLSI Chengyu Hu, Qinghua Duan, Liran Hu, Peng Lu, Zhengjie Li, Meng Yang, Jian Wang, Jinmei Lai
2019	—	`conf`	An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. ACM Great Lakes Symposium on VLSI Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Chengyu Hu, Jian Wang, Jinmei Lai
2019	—	`conf`	An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform. ASICON Jiafeng Liu, Zhiyin Lu, Xie Xie, Jian Wang, Jinmei Lai
2019	—	`conf`	An FPGA-based log-structure Flash memory system for space exploration. ASICON Huanlin Luo, Yunbo Liu, Hai Ren, Tiantian Zhang, Jian Wang, Jinmei Lai
2019	—	`conf`	Balance of memory footprint and runtime for high-density routing in large-scale FPGAs. ASICON Wei Liu, Weilin Cong, Chengyu Hu, Peng Lu, Jinmei Lai
2019	—	`conf`	Design and implementation of Serial ATA pbysical layer on FPGA. ASICON Xie Xie, Qinghua Duan, Jiafeng Liu, Jian Wang, Jinmei Lai
2019	—	`conf`	Research on Area Modeling Methodology for FPGA Interconnect Circuits. ASICON Yunbing Pang, Jiqing Xu, Zhiyin Lu, Zhengjie Li, Yufan Zhang, Jinmei Lai
2019	A	`conf`	Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. FPGA Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai
2018	J	`jnl`	A SA-based parallel method for FPGA placement. IEICE Electron. Express Chengyu Hu, Peng Lu, Meng Yang, Jian Wang, Jinmei Lai
2018	J	`jnl`	Design of a power efficient self-adaptive LVDS driver. IEICE Electron. Express Hanyang Xu, Jian Wang, Jinmei Lai
2017	—	`conf`	A deep research on the chip verification platform based on network. ASICON Chuanliang Kang, Pei Yang, Jian Wang, Jinmei Lai
2017	—	`conf`	FPGA-based convolution neural network for traffic sign recognition. ASICON Yuchen Yao, Zhiqian Zhang, Zhen Yang, Jian Wang, Jinmei Lai
2017	—	`conf`	Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration. ASICON Jiaqi Gu, Ruoyao Wang, Jian Wang, Jinmei Lai, Qinghua Duan
2016	J	`jnl`	A universal automatic on-chip measurement of FPGA's internal setup and hold times. IEICE Electron. Express Yuanlong Xiao, Jian Wang, Jinmei Lai
2016	J	`jnl`	Prototyping design of a flexible DSP block with pipeline structure for FPGA. IEICE Electron. Express Hanyang Xu, Jian Wang, Jinmei Lai
2016	A	`conf`	Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only). FPGA Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai
2015	J	`jnl`	A new automatic method for testing interconnect resources in FPGAs based on general routing matrix. IEICE Electron. Express Zhen Yang, Chuanzeng Liang, Jian Wang, Jinmei Lai
2015	—	`conf`	A power efficient current-mode differential driver for FPGAs. ASICON Yuanlong Xiao, Jian Wang, Jinmei Lai
2015	—	`conf`	FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique. ASICON Yuanpei Gao, Haijiang Ye, Jian Wang, Jinmei Lai
2014	J	`jnl`	An Architecture Independent Packing Method for LUT-based Commercial FPGA. J. Comput. Meng Yang, Jinmei Lai, A. E. A. Almaini
2014	A	`conf`	Novel FPGA clock network with low latency and skew (abstract only). FPGA Lei Li, Jian Wang, Jinmei Lai
2013	—	`conf`	A high-resolution TDC implemented in a 90nm process FPGA. ASICON Jinmei Lai, Yanquan Luo, Qi Shao, Lichun Bao, Xueling Liu
2013	A	`conf`	A novel multithread routing method for FPGAs (abstract only). FPGA Chun Zhu, Qiuli Li, Jian Wang, Jinmei Lai
2013	B	`conf`	A novel net-partition-based multithread FPGA routing method. FPL Chun Zhu, Jian Wang, Jinmei Lai
2013	A	`conf`	FPGA bitstream compression and decompression using LZ and golomb coding (abstract only). FPGA Jinsong Mao, Hao Zhou, Haijiang Ye, Jinmei Lai
2013	—	`conf`	Improved unified interconnect unit for high speed and scalable FPGA. ASICON Lei Li, Jian Wang, Jinmei Lai
2013	J	`jnl`	Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions. J. Comput. Meng Yang, Jiarong Tong, Jinmei Lai
2013	J	`jnl`	Optimisation of Mixed Polarity Reed-Muller Functions. J. Softw. Meng Yang, Jinmei Lai
2013	—	`conf`	The timing control design of 65nm block RAM in FPGA. ASICON Xinrui Zhang, Jian Wang, Dan Chen, Jinmei Lai, Lichun Bao, Xueling Liu
2013	—	`conf`	Weight-based FPGA placement algorithm with wire effect considered. ASICON Huagang Li, Jian Wang, Jinmei Lai
2013	B	`conf`	Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD. FPL Meng Yang, Jinmei Lai, Jiarong Tong
2012	A	`conf`	A novel full coverage test method for CLBs in FPGA (abstract only). FPGA Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai
2012	J	`jnl`	A novel memristor-based rSRAM structure for multiple-bit upsets immunity. IEICE Electron. Express Liyun Wang, Chun Zhang, Liguang Chen, Jinmei Lai, Jiarong Tong
2011	—	`conf`	A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain. ASICON Zhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai
2011	—	`conf`	FPGA interconnect timing library based on the statistical method. ASICON Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai
2011	—	`conf`	Research on design method of scalable Configurable IP Core. AHS Lei Li, Jian Wang, Yuan Wang, Jinmei Lai
2011	—	`conf`	The design and verification of SEU-hardened configurable DFF. ASICON Xinrui Zhang, Liguang Chen, Liyun Wang, Jian Wang, Jinmei Lai
2009	—	`conf`	A Flexible Bit-Stream Level Evolvable Hardware Platform Based on FPGA. AHS HuaQiu Yang, Liguang Chen, Shaoteng Liu, HaiXiang Bu, Yuan Wang, Jinmei Lai
2009	—	`conf`	A delay-optimized universal FPGA routing architecture. ASP-DAC Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Wang, Jiarong Tong
2009	A	`conf`	A novel minloop SB design to improve FPGA routability. FPGA JIanDe Yu, Jinmei Lai
2008	—	`conf`	A high-performance reconfigurable 2-D transform architecture for H.264. ICECS Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min
2008	J	`jnl`	A high-performance reconfigurable VLSI architecture for vbsme in H.264. IEEE Trans. Consumer Electron. Wei Cao, Hui Hou, Jiarong Tong, Jinmei Lai, Hao Min
2008	—	`conf`	A novel dynamic reconfigurable VLSI architecture for H.264 transforms. APCCAS Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min
2008	—	`conf`	Design and implementation of the configuration circuit for FDP FPGA. APCCAS Yabin Wang, Jing Xie, Jinmei Lai, Jiarong Tong
2008	—	`conf`	High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform. ICECS Hui Hou, Wei Cao, Fan-jiong Zhang, Jinmei Lai, Jiarong Tong
2005	—	`conf`	A design of high speed double precision floating point adder using macro modules. ASP-DAC Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li
2005	—	`conf`	Design of A 2.4-GHz integrated frequency synthesizer. ASP-DAC Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun
2003	—	`conf`	Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. ASP-DAC Xinyu Wu, Zaiman Chen, Jinmei Lai, Qianling Zhang, Omar Wing, Junyan Ren