Jinian Bian - RankMe

86 papers A* 1A 4B 3C 12Misc 1Journal 18Unranked 46

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow. ACM Trans. Reconfigurable Technol. Syst. Kang Zhao, Yuchun Ma, Ruining He, Jixing Zhang, Ning Xu, Jinian Bian
2013	C	`conf`	Automatic enhanced CDFG generation based on runtime instrumentation. CSCWD Zhongda Yuan, Yuchun Ma, Jinian Bian, Kang Zhao
2013	Misc	`conf`	Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits. FCCM Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian
2013	—	`conf`	Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs. ASICON Jixin Zhang, Ning Xu, Yuchun Ma, Yu Wang, Jinian Bian
2013	C	`conf`	Efficient custom instruction generation based on characterizing of basic blocks. CSCWD Guoqiang Liang, Yuchun Ma, Kang Zhao, Jinian Bian
2013	B	`conf`	FPGA IP protection by binding Finite State Machine to Physical Unclonable Function. FPL Jiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian
2013	—	`conf`	Incremental 3D NoC synthesis based on physical-aware router merging algorithm. ASICON YuanYuan Li, Ning Xu, Yuchun Ma, Jinian Bian
2013	—	`conf`	RALP: Reconvergence-aware layer partitioning for 3D FPGAs. ReConFig Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian
2013	J	`jnl`	Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. J. Circuits Syst. Comput. Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian
2012	A	`conf`	ISBA: An independent set-based algorithm for automated partial reconfiguration module generation. ICCAD Ruining He, Yuchun Ma, Kang Zhao, Jinian Bian
2012	—	`conf`	PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. ARC Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian
2012	J	`jnl`	Pruning-Based Trace Signal Selection Algorithm for Data Acquisition in Post-Silicon Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kang Zhao, Jinian Bian
2012	—	`conf`	RAW Introduction. IPDPS Workshops Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner
2012	—	`conf`	SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator. IPDPS Workshops Zhongda Yuan, Yuchun Ma, Jinian Bian
2012	J	`jnl`	UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan
2011	C	`conf`	A fast recursive detailed routing algorithm for hierarchical FPGAs. CSCWD Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai
2011	J	`jnl`	Buffer Planning for IP Placement Using Sliced-LFF. VLSI Design Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto
2011	C	`conf`	Instruction-level hardware/software partition through DFG exploration. CSCWD Kang Zhao, Jinian Bian
2011	J	`jnl`	Processor Accelerator Customization through Data Flow Graph Exploration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kang Zhao, Jinian Bian
2011	—	`conf`	Pruning-based trace signal selection algorithm. ASP-DAC Kang Zhao, Jinian Bian
2010	—	`conf`	A low power clock network placement framework. ISQED Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian
2010	C	`conf`	An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. CSCWD Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian
2010	A	`conf`	Behavioral level dual-vth design for reduced leakage power with thermal awareness. DATE Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian
2010	—	`conf`	Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
2010	J	`jnl`	Multilevel Optimization for Large-Scale Hierarchical FPGA Placement. J. Comput. Sci. Technol. Hui Dai, Qiang Zhou, Jinian Bian
2010	A	`conf`	Mutation-based diagnostic test generation for hardware design error diagnosis. ITC Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong
2010	—	`conf`	Peeling algorithm for custom instruction identification. APCCAS Kang Zhao, Jinian Bian
2010	—	`ed.`	Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China FPT Jinian Bian, Qiang Zhou, Peter Athanas, Yajun Ha, Kang Zhao
2010	—	`conf`	Wirelength-driven force-directed 3D FPGA placement. ACM Great Lakes Symposium on VLSI Wentao Sui, Sheqin Dong, Jinian Bian
2009	—	`conf`	An approach to synthesis delay semantics in VHDL. CAD/Graphics Lixin Cheng, Jinian Bian, Yunyun Liu
2009	—	`conf`	Cell shifting aware of wirelength and overlap. ISQED Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong
2009	J	`jnl`	Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong, Kang Zhao
2009	—	`conf`	Fast placement for large-scale hierarchical FPGAs. CAD/Graphics Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
2009	—	`conf`	Global density smoothing technique for analytical placement algorithm. CAD/Graphics Dawei Liu, Qiang Zhou, Jinian Bian, Yanming Jia
2009	J	`jnl`	Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian
2009	—	`conf`	Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. ASP-DAC Junbo Yu, Qiang Zhou, Jinian Bian
2009	J	`jnl`	Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2009	C	`conf`	Random stimulus generation with self-tuning. CSCWD Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong
2009	—	`conf`	Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints. ASP-DAC Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao
2008	J	`jnl`	A cooperative universal data model platform for the data-centric electronic system-level design. Adv. Eng. Informatics Kun Tong, Jinian Bian, Haili Wang
2008	A	`conf`	A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
2008	—	`conf`	Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. ISQED Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2008	C	`conf`	Cache miss reduction through hardware-assisted loop optimization. CSCWD Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto
2008	J	`jnl`	Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2008	J	`jnl`	Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2008	—	`conf`	HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ACM Great Lakes Symposium on VLSI Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2008	—	`conf`	Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian
2008	B	`conf`	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
2007	C	`conf`	A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. CSCWD Kang Zhao, Jinian Bian, Sheqin Dong
2007	C	`conf`	A Management System of Metropolis Energy Information. CSCWD Hui Zhang, Jinian Bian
2007	—	`conf`	An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
2007	—	`conf`	EHSAT Modeling from Algorithm Description for RTL Model Checking. ATS Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao
2007	A*	`conf`	EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. DAC Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao
2007	J	`jnl`	Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2007	—	`conf`	Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. ISVLSI Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai
2007	—	`conf`	Power-driven Real-time System Design with Energy Efficiency via ISA Customization. CAD/Graphics Chenqian Jiang, Jinian Bian, Kang Zhao
2007	—	`conf`	VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR. CAD/Graphics Yanhua Wang, Qiang Zhou, Jinian Bian, Junhua Qu
2006	—	`conf`	A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. APCCAS Kang Zhao, Jinian Bian
2006	—	`conf`	A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. JCIS Kang Zhao, Jinian Bian, Sheqin Dong
2006	J	`jnl`	A novel collaborative scheme of simulation and model checking for system properties verification. Comput. Ind. Ming Zhu, Jinian Bian, Weimin Wu
2006	C	`conf`	AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design. CSCWD Yawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu
2006	—	`conf`	An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design. CSCWD (Selected Papers) Yawen Niu, Jinian Bian, Haili Wang, Kun Tong
2006	—	`conf`	Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving. CSCWD (Selected Papers) Shujun Deng, Weimin Wu, Jinian Bian
2006	C	`conf`	Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving. CSCWD Shujun Deng, Weimin Wu, Jinian Bian
2006	J	`jnl`	Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
2006	—	`conf`	From Software to Hardware - A Novel TLM Auto-Generating Method. APCCAS Liang Zhu, Jinian Bian
2006	J	`jnl`	Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2006	—	`conf`	High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization. APCCAS Zhen Zhao, Jinian Bian, Zhipeng Liu, Yunfeng Wang, Kang Zhao
2006	—	`conf`	Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2006	C	`conf`	Universal data model platform: the data-centric evolution for system level codesign. CSCWD Kun Tong, Jinian Bian, Haili Wang
2005	—	`conf`	A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. ICESS Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu
2005	—	`conf`	A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
2005	—	`conf`	Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs. CSCWD (2) Jianzhou Zhao, Jinian Bian, Weimin Wu
2005	—	`conf`	HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. FPT Feng Lin, Haili Wang, Jinian Bian
2005	—	`conf`	Interconnect delay optimization via high level re-synthesis after floorplanning. ISCAS (6) Yunfeng Wang, Jinian Bian, Xianlong Hong
2005	—	`conf`	System-level architectural exploration using allocation-on-demand technique. ASP-DAC Qiang Wu, Jinian Bian, Hongxi Xue
2005	—	`conf`	iTuCoMe: HCDFG-based incremental tuning HW/SW co-design methodology for multi-level exploration. CSCWD (2) Haili Wang, Jinian Bian, Qiang Wu, Yunfeng Wang
2004	—	`conf`	A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design. ICESS Qiang Wu, Jinian Bian, Hongxi Xue
2004	—	`conf`	CA-Ex: A Tuning-Incremental Methodology for Communication Architectures in Embedded Systems. ICESS Haili Wang, Jinian Bian, Yawen Niu, Kun Tong, Yunfeng Wang
2004	—	`conf`	Model Optimization Techniques in a Verification Platform for Classified Properties. ICESS Ming Zhu, Jinian Bian, Weimin Wu
2004	B	`conf`	PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie. COMPSAC Jianzhou Zhao, Jinian Bian, Weimin Wu
2003	—	`conf`	Property Classification for Functional Verification Based. Asian Test Symposium Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue
2002	J	`jnl`	Accelerating Logic Rewiring Using Implication Analysis Tree. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chin Ngai Sze, Wangning Long, Yu-Liang Wu, Jinian Bian
2000	—	`conf`	IBAW: an implication-tree based alternative-wiring logic transformation algorithm. ASP-DAC Wangning Long, Yu-Liang Wu, Jinian Bian
1999	—	`conf`	FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. ASP-DAC Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong
1997	—	`conf`	VIDE: a visual VHDL integrated design environment. ASP-DAC Jinian Bian, Hongxi Xue, Ming Su