Jinghai Wang

14 papers A* 1A 3Journal 7Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
SynapseHD: A unified training framework for bridging spiking neural networks and hyperdimensional computing.
Neurocomputing
Lingfeng Zhou, Huiyao Wang, Bohan Wang, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2025 — conf
A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits.
ISQED
Bohan Wang, Zeyang Xu, Lingfeng Zhou, Huiyao Wang, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2025 J jnl
ASNA-Flow: An Efficient Asynchronous Neuromorphic Accelerator for Real-Time Event-Based Optical Flow.
IEEE Trans. Very Large Scale Integr. Syst.
Jinghai Wang, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu, Shanlin Xiao
2025 J jnl
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS.
IEEE Trans. Very Large Scale Integr. Syst.
Jinghai Wang, Shanlin Xiao, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu
2025 A conf
FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage Variation.
DATE
Xiangyu Li, Weichong Chen, Ruida Hong, Jinghai Wang, Ningyuan Yin, Zhiyi Yu
2025 — conf
SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks.
ASP-DAC
Bo Li, Yue Liu, Wei Liu, Jinghai Wang, Xiao Huang, Zhiyi Yu, Shanlin Xiao
2025 A conf
Stair-LIF: Boosting the Representation of Spiking Neural Networks with Learnable Incremental Multi-Threshold Neurons.
ICME
Jilong Luo, Yinsheng Chen, Yue Liu, Jinghai Wang, Zhiyi Yu, Shanlin Xiao
2025 A* conf
Towards In-Situ Neuromorphic Computing Architecture for Event Stream Super-Resolution.
DAC
Yihe Yu, Bo Li, Kexin Huang, Wei Liu, Jinghai Wang, Yue Liu, Zhiyi Yu, Shanlin Xiao
2024 A conf
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint.
DATE
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 — conf
An FPGA-based QDI Asynchronous Circuits Design Methodology.
ICTA
Guangyao Lin, Jinghai Wang, Zeyang Xu, Zhiyi Yu, Shanlin Xiao
2024 J jnl
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension.
IEEE Trans. Very Large Scale Integr. Syst.
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 J jnl
LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift.
IEEE Trans. Circuits Syst. II Express Briefs
Huiyao Wang, Shanlin Xiao, Lingfeng Zhou, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2024 J jnl
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint.
IEEE Trans. Very Large Scale Integr. Syst.
Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu
2014 J jnl
Hybrid Implicit Iteration Process for a Finite Family of Non-Self-Nonexpansive Mappings in Uniformly Convex Banach Spaces.
J. Appl. Math.
Qiaohong Jiang, Jinghai Wang, Jian-Hua Huang