Jingcheng Zhuang

17 papers C 1Journal 8Unranked 8
YearRankTypeTitle / Venue / Authors
2015 J jnl
Design of Spur-Free ΣΔ Frequency Tuning Interface for Digitally Controlled Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Jingcheng Zhuang, Khurram Waheed, Robert Bogdan Staszewski
2014 J jnl
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction.
Inf. Media Technol.
Jingcheng Zhuang, Robert Bogdan Staszewski
2014 J jnl
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction.
IPSJ Trans. Syst. LSI Des. Methodol.
Jingcheng Zhuang, Robert Bogdan Staszewski
2013 — conf
Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL.
ECCTD
Jingcheng Zhuang, Robert Bogdan Staszewski
2012 — conf
A low-power all-digital PLL architecture based on phase prediction.
ICECS
Jingcheng Zhuang, Robert Bogdan Staszewski
2011 J jnl
Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End.
IEEE Trans. Circuits Syst. II Express Briefs
Jingcheng Zhuang, Bruce Andrew Doyle, Emerson S. Fang
2011 J jnl
Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers.
IEEE Trans. Circuits Syst. II Express Briefs
Jingcheng Zhuang
2010 J jnl
A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jingcheng Zhuang, Khurram Waheed, Robert Bogdan Staszewski
2009 J jnl
A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application.
IEEE Trans. Very Large Scale Integr. Syst.
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2007 — conf
A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS.
CICC
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
2006 — conf
A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider.
CCECE
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2006 J jnl
A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction.
IEEE Trans. Circuits Syst. II Express Briefs
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2006 — conf
A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System.
SoCC
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2006 — conf
An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur.
CICC
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2006 C conf
An eye detection technique for clock and data recovery applications.
ISCAS
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
2005 — conf
A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO.
Circuits, Signals, and Systems
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
2003 — conf
A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer.
CICC
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski