Jing Ye - RankMe

99 papers A* 5A 17B 5C 4Misc 3Journal 37Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification. CoRR Yonghao Wang, Jiaxin Zhou, Yang Yin, Hongqin Lyu, Zhiteng Chao, Wenchao Ding, Jing Ye, Tiancheng Wang, Huawei Li
2026	J	`jnl`	Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures. CoRR Zizhen Liu, Fangzhiyi Wang, Mengdi Wang, Jing Ye, Hayden Kwok-Hay So, Cheng Liu, Huawei Li
2026	J	`jnl`	On the Vulnerability of FHE Computation to Silent Data Corruption. CoRR Jianan Mu, Ge Yu, Zhaoxuan Kan, Song Bian, Liang Kong, Zizhen Liu, Cheng Liu, Jing Ye, Huawei Li
2026	J	`jnl`	Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction. CoRR Jiaping Tang, Jianan Mu, TianYun Ma, Zhiteng Chao, Jing Ye, Huawei Li
2025	J	`jnl`	A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. Integr. Zhiteng Chao, Xindi Zhang, JunYing Huang, Zizhen Liu, Yixuan Zhao, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li
2025	A*	`conf`	EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components. DAC Mingjun Wang, Hui Wang, Jianan Mu, Xinyu Zhang, Bin Sun, Yihan Wen, Zizhen Liu, Feng Gu, Jun Gao, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li
2025	A	`conf`	ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. DATE Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2025	J	`jnl`	ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. CoRR Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shenwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2025	—	`conf`	ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. ASP-DAC Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li
2025	J	`jnl`	Extend IVerilog to Support Batch RTL Fault Simulation. CoRR Jiaping Tang, Jianan Mu, Zizhen Liu, Zhiteng Chao, Jing Ye, Huawei Li
2025	J	`jnl`	Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware. CoRR Jianan Mu, Mingyu Shi, Yining Wang, Tianmeng Yang, Bin Sun, Xing Hu, Jing Ye, Huawei Li
2025	Misc	`conf`	HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. VTS Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li
2025	J	`jnl`	InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning. CoRR Bin Sun, Rengang Zhang, Zhiteng Chao, Zizhen Liu, Jianan Mu, Jing Ye, Huawei Li
2025	A*	`conf`	MOSS: Multi-Modal Representation Learning on Sequential Circuits. DAC Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, Huawei Li
2025	J	`jnl`	Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation. ACM Trans. Design Autom. Electr. Syst. Zhiteng Chao, Feng Gu, JunYing Huang, Wenjie Li, Jing Ye, Huawei Li, Xiaowei Li
2025	J	`jnl`	ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction. CoRR Bin Sun, Jingyi Zhou, Jianan Mu, Zhiteng Chao, Tianmeng Yang, Ziyue Xu, Jing Ye, Huawei Li
2025	A*	`conf`	PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT. DAC Zhiteng Chao, Xindi Zhang, Xinyu Zhang, Jianan Mu, Zizhen Liu, Shengwen Liang, Shaowei Cai, Jing Ye, Xiaowei Li, Huawei Li
2025	A	`conf`	RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule. ICCAD Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li
2025	J	`jnl`	RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule. CoRR Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li
2025	A	`conf`	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration. ITC Zhiteng Chao, Rengang Zhang, Feng Gu, Hongqin Lyu, Bin Sun, Wenxing Li, Zizhen Liu, Jianan Mu, Jing Ye, Xiaowei Li, Huawei Li
2025	J	`jnl`	Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT. CoRR Zhiteng Chao, Yonghao Wang, Xinyu Zhang, Jiaxin Zhou, Tenghui Hua, Husheng Han, Tianmeng Yang, Jianan Mu, Bei Yu, Rui Zhang, Jing Ye, Huawei Li
2024	B	`conf`	A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. ASPDAC Zhiteng Chao, Xindi Zhang, JunYing Huang, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li
2024	B	`conf`	A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. ETS Han Yan, Shuai Chen, JunYing Huang, Jing Ye, Huawei Li, Xiaowei Li
2024	—	`conf`	A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. ITC-Asia Zhiteng Chao, Qinluan Dai, Jiale Li, Zizhen Liu, Wenxing Li, Hongqin Lyu, Jing Ye, Huawei Li, Xiaowei Li
2024	—	`conf`	Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. ATS Jiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye, Xiaowei Li, Huawei Li
2024	A*	`conf`	Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. DAC Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li
2024	A	`conf`	DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. ICCAD Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li
2024	—	`conf`	Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262. ITC-Asia Mingjun Wang, Hui Wang, Jianan Mu, Zizhen Liu, Jun Gao, Jing Ye, Huawei Li, Xiaowei Li
2024	J	`jnl`	SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. IEEE Trans. Inf. Forensics Secur. Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li
2023	—	`conf`	A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. ATS Zhiteng Chao, Senlin Wang, Pengyu Tian, Shuwen Yuan, Huawei Li, Jing Ye, Xiaowei Li
2023	J	`jnl`	A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Yuan Cao, Wanyi Liu, Yue Zheng, Shuai Chen, Jing Ye, Lei Qian, Chip-Hong Chang
2023	—	`conf`	A Template Attack on Reduction Without Reference Device on Kyber. ATS Yipei Yang, JunYing Huang, Zongyue Wang, Jing Ye, Zihao Sun, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2023	J	`jnl`	Chosen ciphertext correlation power analysis on Kyber. Integr. Yipei Yang, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2023	—	`conf`	Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design. ATS Jianan Mu, Huajie Tan, Shuai Chen, Min Cai, Jing Ye, Huawei Li, Xiaowei Li
2023	J	`jnl`	DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning. J. Supercomput. Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2023	A	`conf`	Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. DATE Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2023	—	`conf`	Message from the Chairs. ATS Huawei Li, Jing Ye, Wei Hu, Jiliang Zhang
2023	B	`conf`	Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. ETS Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li
2023	J	`jnl`	SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks. CoRR Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li
2023	J	`jnl`	Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li
2022	—	`conf`	A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. ASP-DAC Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao
2022	J	`jnl`	Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit. IEEE Trans. Very Large Scale Integr. Syst. Zhen Wang, Guofa Zhang, Peng Liu, Jing Ye, Jianhui Jiang
2022	J	`jnl`	An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Yuan Cao, Yanze Wu, Wen Wang, Xu Lu, Shuai Chen, Jing Ye, Chip-Hong Chang
2022	J	`jnl`	DHSA: Efficient Doubly Homomorphic Secure Aggregation for Cross-silo Federated Learning. CoRR Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2022	J	`jnl`	Entropy Sources Based on Silicon Chips: True Random Number Generator and Physical Unclonable Function. Entropy Yuan Cao, Wanyi Liu, Lan Qin, Bingqiang Liu, Shuai Chen, Jing Ye, Xianzhao Xia, Chao Wang
2022	—	`conf`	Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. ISOCC Yixiao Chen, Jinfeng Song, Shuai Chen, Yuan Cao, Jing Ye, Huawei Li, Xiaowei Li, Xin Lou, Enyi Yao
2022	A	`conf`	SASH: Efficient secure aggregation based on SHPRG for federated learning. UAI Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2021	—	`conf`	ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption. ATS Ning Lin, Xiaoming Chen, Chunwei Xia, Jing Ye, Xiaowei Li
2021	J	`jnl`	Efficient Secure Aggregation Based on SHPRG For Federated Learning. CoRR Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li
2021	J	`jnl`	Practical Attacks on Deep Neural Networks by Memory Trojaning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xing Hu, Yang Zhao, Lei Deng, Ling Liang, Pengfei Zuo, Jing Ye, Yingyan Lin, Yuan Xie
2021	—	`conf`	Reliability Evaluation of Approximate Arithmetic Circuits Based on Signal Probability. ITC-Asia Zhen Wang, Guofa Zhang, Jing Ye, Jianhui Jiang
2020	—	`conf`	HRAE: Hardware-assisted Randomization against Adversarial Example Attacks. ATS Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang
2020	J	`jnl`	INOR - An Intelligent noise reduction method to defend against adversarial audio examples. Neurocomputing Qingli Guo, Jing Ye, Yiran Chen, Yu Hu, Yazhu Lan, Guohe Zhang, Xiaowei Li
2020	J	`jnl`	MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. IEEE Access Qingli Guo, Jing Ye, Yu Hu, Guohe Zhang, Xiaowei Li, Huawei Li
2020	—	`conf`	Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. ATS Yixuan Zhao, Zhiteng Chao, Jing Ye, Wen Wang, Yuan Cao, Shuai Chen, Xiaowei Li, Huawei Li
2020	—	`conf`	Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. ACM Great Lakes Symposium on VLSI Qingli Guo, Jing Ye, Jiliang Zhang, Yu Hu, Xiaowei Li, Huawei Li
2020	—	`conf`	Privacy Threats and Protection in Machine Learning. ACM Great Lakes Symposium on VLSI Jiliang Zhang, Chen Li, Jing Ye, Gang Qu
2020	Misc	`conf`	Sequence Triggered Hardware Trojan in Neural Network Accelerator. VTS Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu
2020	—	`conf`	Survey: Hardware Trojan Detection for Netlist. ATS Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu
2019	—	`conf`	Implementation of Parametric Hardware Trojan in FPGA. ITC-Asia Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu
2019	—	`conf`	Instruction Vulnerability Test and Code Optimization Against DVFS Attack. ITC-Asia JunYing Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang
2019	A	`conf`	Memory Trojan Attack on Neural Network Accelerators. DATE Yang Zhao, Xing Hu, Shuangchen Li, Jing Ye, Lei Deng, Yu Ji, Jianyu Xu, Dong Wu, Yuan Xie
2019	J	`jnl`	PUFPass: A password management mechanism based on software/hardware codesign. Integr. Qingli Guo, Jing Ye, Bing Li, Yu Hu, Xiaowei Li, Yazhu Lan, Guohe Zhang
2019	J	`jnl`	Scan Chain Based Attacks and Countermeasures: A Survey. IEEE Access Xiaowei Li, Wenjie Li, Jing Ye, Huawei Li, Yu Hu
2019	C	`conf`	iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. IOLTS Kuozhong Zhang, JunYing Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang
2018	—	`conf`	Bias PUF based Secure Scan Chain Design. AsianHOST Wenjie Li, Jing Ye, Xiaowei Li, Huawei Li, Yu Hu
2018	J	`jnl`	Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jing Ye, Qingli Guo, Yu Hu, Xiaowei Li
2018	J	`jnl`	Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach. Sci. China Inf. Sci. Xiaowei Li, Guihai Yan, Jing Ye, Ying Wang
2018	—	`conf`	Grey Zone in Pre-Silicon Hardware Trojan Detection. ITC-Asia Jing Ye, Yipei Yang, Yue Gong, Yu Hu, Xiaowei Li
2018	—	`conf`	Hardware Trojan in FPGA CNN Accelerator. ATS Jing Ye, Yu Hu, Xiaowei Li
2018	Misc	`conf`	Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. VTS Jing Ye, Qingli Guo, Yu Hu, Huawei Li, Xiaowei Li
2018	—	`conf`	PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model. ATS Qingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
2018	J	`jnl`	RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving. IEEE Robotics Autom. Lett. Yiming Zeng, Yu Hu, Shice Liu, Jing Ye, Yinhe Han, Xiaowei Li, Ninghui Sun
2018	A	`conf`	VarNet: Exploring Variations for Unsupervised Video Prediction. IROS Beibei Jin, Yu Hu, Yiming Zeng, Qiankun Tang, Shice Liu, Jing Ye
2017	A	`conf`	Fault diagnosis of arbiter physical unclonable function. DATE Jing Ye, Qingli Quo, Yu Hu, Xiaowei Li
2017	A	`conf`	GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image. IROS Yiming Zeng, Yu Hu, Shice Liu, Qiankun Tang, Jing Ye, Xiaowei Li
2017	J	`jnl`	Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Weina Lu, Yu Hu, Jing Ye, Xiaowei Li
2017	J	`jnl`	LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization. IEICE Trans. Inf. Syst. Yu Hu, Jing Ye, Zhiping Shi, Xiaowei Li
2017	B	`conf`	Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators. FPL Weina Lu, Wenyan Lu, Jing Ye, Yu Hu, Xiaowei Li
2017	—	`conf`	Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. AsianHOST Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
2017	C	`conf`	Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. IOLTS Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
2017	J	`jnl`	Power-Utility-Driven Write Management for MLC PCM. ACM J. Emerg. Technol. Comput. Syst. Bing Li, Yu Hu, Ying Wang, Jing Ye, Xiaowei Li
2017	C	`conf`	VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance. IOLTS Jing Ye, Yu Hu, Xiaowei Li
2016	A	`conf`	DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only). FPGA Jing Ye, Yu Hu, Xiaowei Li
2016	—	`conf`	Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm. ATS Qingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
2016	A*	`conf`	POSTER: Attack on Non-Linear Physical Unclonable Function. CCS Jing Ye, Yu Hu, Xiaowei Li
2016	—	`conf`	RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack. AsianHOST Jing Ye, Yu Hu, Xiaowei Li
2016	B	`conf`	TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. FPL Weina Lu, Yu Hu, Jing Ye, Xiaowei Li
2015	J	`jnl`	Diagnosis and Layout Aware (DLA) Scan Chain Stitching. IEEE Trans. Very Large Scale Integr. Syst. Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2015	C	`conf`	OPUF: Obfuscation logic based physical unclonable function. IOLTS Jing Ye, Yu Hu, Xiaowei Li
2014	J	`jnl`	Diagnose Failures Caused by Multiple Locations at a Time. IEEE Trans. Very Large Scale Integr. Syst. Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang
2013	A	`conf`	Capturing post-silicon variation by layout-aware path-delay testing. DATE Xiaolin Zhang, Jing Ye, Yu Hu, Xiaowei Li
2013	A	`conf`	Diagnosis and Layout Aware (DLA) scan chain stitching. ITC Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2011	A	`conf`	On diagnosis of multiple faults using compacted responses. DATE Jing Ye, Yu Hu, Xiaowei Li
2010	A	`conf`	Diagnosis of multiple arbitrary faults with mask and reinforcement effect. DATE Jing Ye, Yu Hu, Xiaowei Li
2010	—	`conf`	Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method. Asian Test Symposium Jing Ye, Xiaolin Zhang, Yu Hu, Xiaowei Li
2008	A	`conf`	Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. ITC Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang
2008	A	`conf`	Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains. ITC Jing Ye, Fei Wang, Yu Hu, Xiaowei Li
2008	—	`conf`	Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis. ATS Fei Wang, Yu Hu, Yu Huang, Jing Ye, Xiaowei Li