Jing Tian

54 papers C 7Journal 32Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Unified Hardware Architecture for Stateful and Stateless Hash-Based Key/Signature Generations.
IACR Cryptol. ePrint Arch.
Yechu Zhang, Yuxuan Chu, Yaodong Wei, Yueqin Dai, Qiu Shen, Jing Tian
2026 J jnl
CrowdGaussian: Reconstructing High-Fidelity 3D Gaussians for Human Crowd from a Single Image.
CoRR
Yizheng Song, Yiyu Zhuang, Qipeng Xu, Haixiang Wang, Jiahe Zhu, Jing Tian, Siyu Zhu, Hao Zhu
2025 J jnl
A Hardware-Friendly Shuffling Countermeasure Against Side-Channel Attacks for Kyber.
IEEE Trans. Circuits Syst. II Express Briefs
Dejun Xu, Kai Wang, Jing Tian
2025 J jnl
An Improved Two-Step Attack on Lattice-Based Cryptography: A Case Study of Kyber.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kai Wang, Dejun Xu, Jing Tian
2025 J jnl
Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece.
IEEE Trans. Circuits Syst. I Regul. Pap.
Haochen Zhang, Xinyuan Qiao, Jing Tian, Suwen Song, Zhongfeng Wang
2025 J jnl
Fast Scloud+: A Fast Hardware Implementation for the Unstructured LWE-based KEM - Scloud+.
IACR Cryptol. ePrint Arch.
Jing Tian, Yaodong Wei, Dejun Xu, Kai Wang, Anyu Wang, Zhiyuan Qiu, Fu Yao, Guang Zeng
2025 J jnl
HRCIM-NTT: An Efficient Compute-in-Memory NTT Accelerator With Hybrid-Redundant Numbers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xu Zhang, Yaodong Wei, Minghao Li, Jing Tian, Zhongfeng Wang
2025 — conf
High-Performance FPGA-Based Accelerator of L-BFGS for 3D Face Reconstruction.
ISVLSI
Haoran Pan, Bohang Xiong, Jing Tian, Shikun Zhang, Hao Zhu, Zhongfeng Wang
2025 — conf
Low-Complexity and High-Performance Accelerator for 3D Gaussian Splatting Preprocessing.
SiPS
Yongzhen Zhang, Jian Gao, Shikun Zhang, Yao Yao, Hao Zhu, Jing Tian
2024 J jnl
A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA.
IACR Cryptol. ePrint Arch.
Jing Tian, Bo Wu, Lang Feng, Haochen Zhang, Zhongfeng Wang
2024 J jnl
A Hardware-Friendly Shuffling Countermeasure Against Side-Channel Attacks for Kyber.
CoRR
Dejun Xu, Kai Wang, Jing Tian
2024 J jnl
An Improved Two-Step Attack on CRYSTALS-Kyber.
CoRR
Kai Wang, Dejun Xu, Jing Tian
2023 J jnl
A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yifeng Song, Xiao Hu, Jing Tian, Zhongfeng Wang
2023 J jnl
AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiao Hu, Jing Tian, Minghao Li, Zhongfeng Wang
2023 — conf
An Efficient Hardware Design for Fast Implementation of HQC.
SOCC
Chen Li, Suwen Song, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç
2023 — conf
Efficient Decryption Architecture for Classic McEliece.
ISQED
Xinyuan Qiao, Suwen Song, Jing Tian, Zhongfeng Wang
2023 C conf
Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications.
ISCAS
Huiyang Xiong, Bohang Xiong, Wenhao Wang, Jing Tian, Hao Zhu, Zhongfeng Wang
2023 J jnl
Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation.
IEEE Trans. Circuits Syst. II Express Briefs
Lun Ou, Danyang Zhu, Jing Tian, Zhongfeng Wang
2023 — conf
High-Throughput Hardware Implementation for Haraka in SPHINCS+.
ISQED
Yueqin Dai, Yifeng Song, Jing Tian, Zhongfeng Wang
2023 J jnl
Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Danyang Zhu, Rongrong Zhang, Lun Ou, Jing Tian, Zhongfeng Wang
2023 J jnl
Low-latency Hardware Architecture for VDF Evaluation in Class Groups.
IEEE Trans. Computers
Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang
2023 J jnl
Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Minghao Li, Jing Tian, Xiao Hu, Zhongfeng Wang
2022 C conf
A High-Speed Codec Architecture for Lagrange Coded Computing.
ISCAS
Bohang Xiong, Jing Tian, Zhongfeng Wang
2022 — conf
An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking.
ISVLSI
Lei Yang, Jing Tian, Bo Wu, Zhongfeng Wang, Hao Ren
2022 J jnl
Efficient Homomorphic Convolution Designs on FPGA for Secure Inference.
IEEE Trans. Very Large Scale Integr. Syst.
Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang
2022 J jnl
Efficient Software Implementation of the SIKE Protocol Using a New Data Representation.
IEEE Trans. Computers
Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl
2022 — conf
High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber.
APCCAS
Minghao Li, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang
2022 J jnl
Low-latency Hardware Architecture for VDF Evaluation in Class Groups.
IACR Cryptol. ePrint Arch.
Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang
2022 C conf
Reduction-Free Multiplication for Finite Fields and Polynomial Rings.
WAIFI
Samira Carolina Oliva Madrigal, Gökay Saldamli, Chen Li, Yue Geng, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç
2021 J jnl
A High-Speed Architecture for the Reduction in VDF Based on a Class Group.
IACR Cryptol. ePrint Arch.
Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang
2021 J jnl
An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes.
IEEE Commun. Lett.
Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2021 — conf
DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography.
ASAP
Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang
2021 J jnl
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Tian, Jun Lin, Zhongfeng Wang
2021 J jnl
High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jing Tian, Bo Wu, Zhongfeng Wang
2021 C conf
High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol.
ISCAS
Yifeng Song, Xiao Hu, Wenhao Wang, Jing Tian, Zhongfeng Wang
2021 C conf
Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers.
ISCAS
Danyang Zhu, Jing Tian, Zhongfeng Wang
2020 — conf
A High-Speed Architecture for the Reduction in VDF Based on a Class Group.
SoCC
Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang
2020 J jnl
A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Suwen Song, Hangxuan Cui, Jing Tian, Jun Lin, Zhongfeng Wang
2020 — conf
A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography.
ISVLSI
Bo Wu, Jing Tian, Xiao Hu, Zhongfeng Wang
2020 — conf
An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group.
APCCAS
Danyang Zhu, Yifeng Song, Jing Tian, Zhongfeng Wang, Haobo Yu
2020 — conf
Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference.
APCCAS
Xiao Hu, Jing Tian, Zhongfeng Wang
2020 J jnl
Faster Software Implementation of the SIKE Protocol Based on A New Data Representation.
IACR Cryptol. ePrint Arch.
Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl
2020 J jnl
High-Speed FPGA Implementation of the SIKE Based on An Ultra-Low-Latency Modular Multiplier.
IACR Cryptol. ePrint Arch.
Jing Tian, Bo Wu, Zhongfeng Wang
2020 J jnl
Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang
2020 J jnl
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch.
Jing Tian, Jun Lin, Zhongfeng Wang
2019 C conf
A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes.
ISCAS
Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2019 J jnl
Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes.
IEEE Access
Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang
2019 J jnl
High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch.
Jing Tian, Zhe Liu, Jun Lin, Zhongfeng Wang, Binjing Li
2019 J jnl
Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders.
IEEE Commun. Lett.
Wenjie Li, Jing Tian, Jun Lin, Zhongfeng Wang
2019 — conf
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes.
ASICON
Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2019 — conf
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography.
SiPS
Jing Tian, Jun Lin, Zhongfeng Wang
2018 J jnl
A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications.
IEEE Trans. Circuits Syst. II Express Briefs
Jing Tian, Jun Lin, Zhongfeng Wang
2018 C conf
An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories.
ISCAS
Jing Tian, Jun Lin, Zhongfeng Wang
2018 — conf
Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding.
APCCAS
Jing Tian, Jun Lin, Zhongfeng Wang