Jing Li

51 papers A* 8A 14C 2Misc 3Journal 18Unranked 6
YearRankTypeTitle / Venue / Authors
2026 A conf
Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds.
FPGA
Ezra Thomas, Jing Li, André DeHon
2026 A ed.
Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2026, Seaside, CA, USA, February 22-24, 2026
FPGA
Jing Li, Grace Zgheib
2025 A ed.
Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2025, Monterey, CA, USA, 27 February 2025 - 1 March 2025
FPGA
Andrew Putnam, Jing Li
2024 J jnl
LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits.
CoRR
Chen-Chia Chang, Yikang Shan, Shaoze Fan, Jing Li, Shun Zhang, Ningyuan Cao, Yiran Chen, Xin Zhang
2023 J jnl
Introduction to the Special Section on FCCM 2022.
ACM Trans. Reconfigurable Technol. Syst.
Jing Li, Martin C. Herbordt
2022 A conf
Revisiting PathFinder Routing Algorithm.
FPGA
Yue Zha, Jing Li
2021 A* conf
Hetero-ViTAL: A Virtualization Stack for Heterogeneous FPGA Clusters.
ISCA
Yue Zha, Jing Li
2021 A* conf
When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs.
ASPLOS
Yue Zha, Jing Li
2020 A* conf
Hyper-Ap: Enhancing Associative Processing Through A Full-Stack Optimization.
ISCA
Yue Zha, Jing Li
2020 J jnl
Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM.
IEEE J. Solid State Circuits
Yue Zha, Etienne Nowak, Jing Li
2020 J jnl
MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory.
ACM Trans. Reconfigurable Technol. Syst.
Jialiang Zhang, Yue Zha, Nicholas Beckwith, Bangya Liu, Jing Li
2020 A* conf
Virtualizing FPGAs in the Cloud.
ASPLOS
Yue Zha, Jing Li
2019 J jnl
Interleaved Composite Quantization for High-Dimensional Similarity Search.
CoRR
Soroosh Khoram, Stephen J. Wright, Jing Li
2019 — conf
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications.
VLSI Circuits
Yue Zha, Etienne Nowak, Jing Li
2019 Misc conf
MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube.
FCCM
Jialiang Zhang, Yang Liu, Gaurav Jain, Yue Zha, Jonathan Ta, Jing Li
2019 J jnl
SysML: The New Frontier of Machine Learning Systems.
CoRR
Alexander Ratner, Dan Alistarh, Gustavo Alonso, David G. Andersen, Peter Bailis, Sarah Bird, Nicholas Carlini, Bryan Catanzaro, Eric S. Chung, Bill Dally, Jeff Dean, Inderjit S. Dhillon, Alexandros G. Dimakis, Pradeep Dubey, Charles Elkan, Grigori Fursin, Gregory R. Ganger, Lise Getoor, Phillip B. Gibbons, Garth A. Gibson, Joseph E. Gonzalez, Justin Gottschlich, Song Han, Kim M. Hazelwood, Furong Huang, Martin Jaggi, Kevin Jamieson, Michael I. Jordan, Gauri Joshi, Rania Khalaf, Jason Knight, Jakub Konecný, Tim Kraska, Arun Kumar, Anastasios Kyrillidis, Jing Li, Samuel Madden, H. Brendan McMahan, Erik Meijer, Ioannis Mitliagkas, Rajat Monga, Derek Gordon Murray, Dimitris S. Papailiopoulos, Gennady Pekhimenko, Theodoros Rekatsinas, Afshin Rostamizadeh, Christopher Ré, Christopher De Sa, Hanie Sedghi, Siddhartha Sen, Virginia Smith, Alex Smola, Dawn Song, Evan Randall Sparks, Ion Stoica, Vivienne Sze, Madeleine Udell, Joaquin Vanschoren, Shivaram Venkataraman, Rashmi Vinayak, Markus Weimer, Andrew Gordon Wilson, Eric P. Xing, Matei Zaharia, Ce Zhang, Ameet Talwalkar
2019 J jnl
TOCO: A Framework for Compressing Neural Network Models Based on Tolerance Analysis.
CoRR
Soroosh Khoram, Jing Li
2019 A conf
Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization.
FPGA
Jialiang Zhang, Jing Li
2018 A conf
Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform.
FPGA
Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li
2018 — conf
Adaptive Quantization of Neural Networks.
ICLR (Poster)
Soroosh Khoram, Jing Li
2018 J jnl
An Alternative Analytical Approach to Associative Processing.
IEEE Comput. Archit. Lett.
Soroosh Khoram, Yue Zha, Jing Li
2018 J jnl
CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection.
IEEE Comput. Archit. Lett.
Yue Zha, Jing Li
2018 A conf
Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform.
FPGA
Jialiang Zhang, Jing Li
2018 A* conf
Efficient Large-Scale Approximate Nearest Neighbor Search on OpenCL FPGA.
CVPR
Jialiang Zhang, Soroosh Khoram, Jing Li
2018 J jnl
Evaluating Row Buffer Locality in Future Non-Volatile Main Memories.
CoRR
Justin Meza, Jing Li, Onur Mutlu
2018 A* conf
Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support.
ASPLOS
Yue Zha, Jing Li
2018 A conf
Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology.
FPGA
Yue Zha, Jing Li
2018 Misc conf
PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGA.
FCCM
Jialiang Zhang, Jing Li
2018 J jnl
Specialization: A New Path Towards Low Power.
J. Low Power Electron.
Yue Zha, Jing Li
2017 A conf
A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only).
FPGA
Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li
2017 Misc conf
Accelerating Large-Scale Graph Analytics with FPGA and HMC.
FCCM
Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li
2017 A conf
Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search.
FPGA
Jialiang Zhang, Soroosh Khoram, Jing Li
2017 — conf
Challenges and Opportunities: From Near-memory Computing to In-memory Computing.
ISPD
Soroosh Khoram, Yue Zha, Jialiang Zhang, Jing Li
2017 J jnl
IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar.
IEEE Comput. Archit. Lett.
Yue Zha, Jing Li
2017 A conf
RRAM-based reconfigurable in-memory computing architecture with hybrid routing.
ICCAD
Yue Zha, Jing Li
2016 A conf
Reconfigurable in-memory computing with resistive memory crossbar.
ICCAD
Yue Zha, Jing Li
2015 C conf
Enabling phase-change memory for data-centric computing: Technology, circuitand system.
ISCAS
Jing Li
2014 J jnl
1 Mb 0.41 µm
IEEE J. Solid State Circuits
Jing Li, Robert K. Montoye, Masatoshi Ishii, Leland Chang
2012 C conf
A case for small row buffers in non-volatile main memories.
ICCD
Justin Meza, Jing Li, Onur Mutlu
2011 J jnl
Phase change memory.
Sci. China Inf. Sci.
Jing Li, Chung Lam
2011 — conf
Post-silicon calibration of analog CMOS using phase-change memory cells.
ESSCIRC
Cheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li, Sangbum Kim, Jonathan E. Proesel, Chung Lam
2010 J jnl
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Li, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy
2010 J jnl
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.
IEEE Trans. Very Large Scale Integr. Syst.
Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy
2009 — conf
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.
ASP-DAC
Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy
2009 J jnl
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jing Li, Kunhyuk Kang, Kaushik Roy
2008 J jnl
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
ACM J. Emerg. Technol. Comput. Syst.
Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy
2008 A* conf
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.
DAC
Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy
2008 — conf
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement.
CICC
Jing Li, Haixin Liu, Sayeef S. Salahuddin, Kaushik Roy
2007 A conf
A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs.
ITC
Jing Li, Swaroop Ghosh, Kaushik Roy
2007 A* conf
High Performance and Low Power Electronics on Flexible Substrate.
DAC
Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy
2007 A conf
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
ISLPED
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh