Jing Jin - RankMe

85 papers C 20Journal 40Unranked 25

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 14-bit 1.4 GS/s current-steering DAC with square-dithered frequency-modulated DEM achieving >60-dBc SFDR in 180 nm CMOS. Microelectron. J. Qiang Pan, Yitao Wang, Jiayi Chen, Yuekang Guo, Jing Jin, Jianjun Zhou
2026	J	`jnl`	A 3-5 V to Sub-1 V DLDO-SC-Sigma Converter With Auxiliary Loop for Efficiency Improvement in High-Density Power Delivery. IEEE J. Solid State Circuits Yuxiang Li, Jing Jin, Yuekang Guo, Jianjun Zhou, Junmin Jiang
2026	J	`jnl`	A 3.2-mW Quad-Core CMOS Class-C VCO Achieving 197.1-dBc/Hz Peak FoM at 0.7-V Supply. IEEE Trans. Circuits Syst. II Express Briefs Sheng Wang, Chao Yang, Jianjun Zhou, Jing Jin
2026	J	`jnl`	A 37-48 GHz Frequency Doubler With >47.8 dBc FRR Utilizing a Staggered Fundamental Suppression Technique. IEEE Trans. Circuits Syst. II Express Briefs Yuyang Chen, Chao Yang, Xiaoming Liu, Jing Jin, Jianjun Zhou
2026	J	`jnl`	A 40-nm CMOS Phase-Tunable Four-Phase Injection-Locked Ring VCO Utilizing Unbalanced Feedforward Topology Achieving -211.1- to -207.3-dBc/Hz FoM IEEE J. Solid State Circuits Huzhi Tang, Yuekang Guo, Jing Jin, Xiaoming Liu, Yi Liu, Zhongyuan Chang, Howard C. Yang, Jianjun Zhou
2026	—	`conf`	A 5-to-1V DLDO-Hybrid-Sigma Converter Achieving Fast Transient for High-Density Power Delivery. ASP-DAC Zizhe Huang, Yuxiang Li, Yuekang Guo, Jing Jin, Jianjun Zhou, Junmin Jiang
2026	J	`jnl`	An IR-UWB Transmitter Using Two-Dimensional Differential Pulse Position Modulation. IEEE Trans. Circuits Syst. II Express Briefs Dingguo Zhang, Chao Yang, Jianjun Zhou, Jing Jin
2025	J	`jnl`	A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Zhaolin Yang, Jing Jin, Xiaoming Liu, Jianjun Zhou
2025	J	`jnl`	A 14-bit 2.6GS/s RF sampling pipelined ADC in 28nm CMOS. Microelectron. J. Hui Zhang, Dawei Dong, Haijun Wang, Dan Li, Yuan Gao, Chaoyi Hu, Hao Xu, Xinlei Song, Jing Jin, Yuekang Guo, Lin Cheng
2025	J	`jnl`	A 25 MHz-BW 81 dB-DR TDC-Based CTDSM With Background Analog-Integration-Based ISI Error Calibration Achieving >8 dB Even-Order Harmonic Suppression. IEEE Trans. Circuits Syst. I Regul. Pap. Tao Zhong, Yuekang Guo, Jianjun Zhou, Hui Zhang, Jing Jin
2025	J	`jnl`	A 470 μW 20 kHz-BW 107.3 dB-SNDR Nested CT DSM Using Negative-R-Based Cross-RC Integrator and Weighted Multi-Threshold MSB-Pass Quantizer. IEEE Trans. Circuits Syst. I Regul. Pap. Jing Jin, Meng Xu, Yuekang Guo, Xiaoming Liu, Nan Sun, Jianjun Zhou
2025	J	`jnl`	A 78.1 dB SNDR 10 MHz-BW continuous-time noise-shaping SAR ADC in 28 nm CMOS. Microelectron. J. Hui Zhang, Yong Li, Dawei Dong, Danben He, Yuan Gao, Jing Jin, Yuekang Guo, Lei Qiu, Zhenrong Li, Lin Cheng
2025	J	`jnl`	A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement. IEEE Trans. Circuits Syst. I Regul. Pap. Ke Wu, Yuekang Guo, Xiaoming Liu, Zhongyuan Chang, Howard C. Yang, Jing Jin, Jianjun Zhou
2025	J	`jnl`	A reconfigurable passive LNA using an N-path switched-capacitor transformer with 2×/3× voltage Gain. Microelectron. J. Zhaolin Yang, Xiaoming Liu, Jing Jin, Jianjun Zhou
2025	J	`jnl`	A two-phase oscillation scheme with direct background correction for VCO-based ADC. Microelectron. J. Tao Zhong, Yuekang Guo, Jing Jin, Jianjun Zhou
2025	C	`conf`	A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator. ISCAS Jinwei Wu, Yuekang Guo, Meng Xu, Lingyan Fan, Jing Jin, Jianjun Zhou
2025	C	`conf`	An EF-CIFF Noise-Shaping SAR ADC with A Joint Dynamic Amplifier, Comparator and Lossless Passive Summer Structure. ISCAS Yuzhi Ai, Yuekang Guo, Zhengyuan Lou, Hui Zhang, Jing Jin, Jianjun Zhou
2024	J	`jnl`	A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaofei Wang, Jing Jin, Xiaoming Liu, Hui Wang, Huzhi Tang, Chao Yang, Yuekang Guo, Tingting Mo, Jianjun Zhou
2024	—	`conf`	A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique. CICC Runtao Huo, Dingguo Zhang, Jing Jin, Jianjun Zhou, Hui Wang
2024	—	`conf`	A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer. CICC Jing Jin, Yuekang Guo, Meng Xu, Xiaoming Liu, Nan Sun, Jianjun Zhou
2024	C	`conf`	A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC. ISCAS Zhengyuan Lou, Meng Xu, Yuekang Guo, Jing Jin, Jianjun Zhou
2024	C	`conf`	Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor. ISCAS Tong Zhang, Dingguo Zhang, Jing Jin, Patrick P. Mercier, Hui Wang
2024	J	`jnl`	TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core. IEEE J. Solid State Circuits Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jing Jin, Jun Yang, Mingoo Seok
2023	C	`conf`	A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces. ISCAS Xiaofei Wang, Jing Jin, Xiaoming Liu, Zhaolin Yang, Shan Wang, Jianjun Zhou
2023	—	`conf`	A 24/48 Gb/s NRZ/PAM-4 Dual-Mode Transmitter with 3-tap FFE in 28 nm CMOS. ASICON Jiaxu Zhou, Jing Jin, Yichao Lin, Shan Wang, Bo Wang, Tingting Mo
2023	—	`conf`	A 30GHz Bidirectional PA/LNA with Transformer-Based Switchable RC Matching Network. ASICON Hanqi Gao, Jing Jin, Zhaolin Yang, Jianjun Zhou, Xiaoming Liu
2023	J	`jnl`	A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization. IEEE J. Solid State Circuits Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2023	J	`jnl`	A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS. Microelectron. J. Chao Yang, Sheng Wang, Xiaoming Liu, Jing Jin, Jianjun Zhou
2023	J	`jnl`	A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. IEEE J. Solid State Circuits Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2023	J	`jnl`	A Compact 0.2-1.6 GHz 20 MHz-Bandwidth Passive-LNA Exploiting an N-Path 1:3 Transformer. IEEE Trans. Circuits Syst. II Express Briefs Minjing Lee, Xiaoming Liu, Zhaolin Yang, Jing Jin, Lin-Sheng Wu
2023	—	`conf`	A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration. MWSCAS Shunyan Wang, Yuekang Guo, Qiang Pan, Xiaoming Liu, Shan Wang, Jing Jin
2023	C	`conf`	A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$. ISCAS Yuekang Guo, Jing Jin, Xiaoming Liu, Zhaolin Yang, Jianjun Zhou
2023	—	`conf`	A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions. MWSCAS Ke Wu, Yuekang Guo, Xiaoming Liu, Jing Jin, Howard C. Yang, Jianjun Zhou
2023	—	`conf`	A Wideband Inductorless LNA Employing Dual-Loop Feedback for Low-Power Applications. ASICON Zhaolin Yang, Jing Jin, Yuyang Chen, Jianjun Zhou, Xiaoming Liu
2023	C	`conf`	An ADPLL with Two-Point Modulation Gain Calibration for 2.4GHz ISM-Band in 40nm CMOS. ISCAS Huzhi Tang, Xiaoming Liu, Chao Yang, Jing Jin
2023	—	`conf`	Fast locking Sampling PLL Using Phase Error Eliminator. ASICON Shengyuan Zhou, Ziyao Xia, Chao Yang, Xiaoming Liu, Sheng Wang, Jing Jin
2023	—	`conf`	Predictive LSB-First Successive Approximation for SAR Analog-to-Digital Converters. MWSCAS Jiayi Chen, Xiaoming Liu, Chao Yang, Jing Jin, Zhongyuan Chang, Jianjun Zhou
2022	J	`jnl`	A 0.023-12 GHz ultra-wideband frequency synthesizer with FOM Microelectron. J. Chao Yang, Xiaoming Liu, Jing Jin, Jianjun Zhou
2022	J	`jnl`	A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Li Ding, Jing Jin, Jianjun Zhou
2022	C	`conf`	A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme. ISCAS Yuekang Guo, Xiaoming Liu, Jing Jin, Jianjun Zhou
2022	J	`jnl`	A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP. IEEE Trans. Circuits Syst. II Express Briefs Chao Yang, Xiaoming Liu, Jing Jin, Yuekang Guo, Jianjun Zhou
2022	J	`jnl`	A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique. Circuits Syst. Signal Process. Ran Bu, Jing Jin, Zhaolin Yang, Yuekang Guo, Jianjun Zhou
2022	—	`conf`	A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration. MWSCAS Ke Wu, Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2022	J	`jnl`	An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC. IEEE Trans. Circuits Syst. I Regul. Pap. Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2021	J	`jnl`	A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS. Microelectron. J. Xiaoming Liu, Jing Jin, Xiaofei Wang, Jianjun Zhou
2021	—	`conf`	A Center Frequency Calibration Technique for Ring VCO Exploiting Delay MWSCAS Yuekang Guo, Qiang Pan, Xiaoming Liu, Jing Jin
2021	C	`conf`	A Ka-Band Quadrature-Hybrid LNA-PS with Gm- Boosting Technique in 40-nm CMOS. ISCAS Zhengqi Xu, Ke Wu, Xiaoming Liu, Chengyuan Liu, Jing Jin, Jianjun Zhou
2021	—	`conf`	A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs. MWSCAS Yanlin He, Yuekang Guo, Jing Jin, Jianjun Zhou
2021	—	`conf`	A Linearization Technique for Ring VCO Exploiting Bulk-Modulation. MWSCAS Qiang Pan, Yuekang Guo, Jing Jin, Jianjun Zhou
2021	—	`conf`	A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC. MWSCAS Yuekang Guo, Jing Jin, Jianjun Zhou
2021	C	`conf`	A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC. ISCAS Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2021	J	`jnl`	A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. Circuits Syst. Signal Process. Mengying Hu, Jing Jin, Yuekang Guo, Xiaoming Liu, Jianjun Zhou
2021	J	`jnl`	A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction. Microelectron. J. Haopeng Kang, Jing Jin, Xiaoming Liu, Xiaofei Wang, Pengli Hong, Jianjun Zhou
2021	J	`jnl`	An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications. Microelectron. J. Li Ding, Ke Wu, Jing Jin, Jianjun Zhou
2021	—	`conf`	An Enhanced SSCP for Frequency Drift Suppressing in SSPLL. ASICON Chenyue Shi, Shengyuan Zhou, Jing Jin
2021	—	`conf`	Analysis of SAR ADC Quantization Error and Nonlinearity in PMCW Automotive Radar. ASICON Tao Zhong, Yuekang Guo, Jing Jin
2020	C	`conf`	A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. ISCAS Ran Wang, Yuekang Guo, Jing Jin, Xiaoming Liu, Naifeng Jing, Jianjun Zhou
2020	J	`jnl`	A Multi-Modulus Fractional Divider With TDC Free Calibration Scheme for Mitigation of TX-VCO Pulling. IEEE Trans. Circuits Syst. LiTong Liu, Jing Jin, Xiaoming Liu, Jianjun Zhou
2020	J	`jnl`	An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance. IEEE Trans. Circuits Syst. Xiaofei Wang, Jing Jin, Xiaoming Liu, Jianjun Zhou
2020	J	`jnl`	An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration. IEEE Trans. Circuits Syst. Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou
2020	C	`conf`	Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. ISCAS Tu Hong, Ning Guan, Chen Yin, Qin Wang, Jianfei Jiang, Jing Jin, Guanghui He, Naifeng Jing
2019	—	`conf`	A 0.0558-mm ASICON Zhigang Li, Xiaofei Wang, Jing Jin
2019	J	`jnl`	A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications. IEEE Trans. Circuits Syst. II Express Briefs Jing Jin, Xiaoming Liu, Jianjun Zhou
2019	—	`conf`	A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration. ASICON Songhao Guo, Li Ding, Jing Jin
2019	—	`conf`	A High-Linear Digital-to-Phase Converter in 40nm CMOS. ASICON Yu Ji, Li Ding, Jing Jin
2019	J	`jnl`	A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. ACM Trans. Design Autom. Electr. Syst. Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing
2019	C	`conf`	A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. ISCAS Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing
2019	—	`conf`	An Optimized Modeling Method for Transformer Design. ASICON Yingying Liang, Xiaoming Liu, Jing Jin
2019	J	`jnl`	Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receivers. IEEE Trans. Circuits Syst. II Express Briefs Jing Jin, Xiaoming Liu, Taotao Yan, Jianjun Zhou
2018	J	`jnl`	16-bit 1-MS/s SAR ADC with foreground digital-domain calibration. IET Circuits Devices Syst. Rui Guan, Jianfeng Xue, Chao Yang, Jing Jin, Jianjun Zhou
2018	C	`conf`	A 28 Gb/s 2-Tap FFE Source-Series-Terminated Transmitter in 22 nm CMOS FDSOI. ISCAS Hanchun Tang, Li Ding, Jing Jin, Jianjun Zhou
2018	C	`conf`	A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse. ISCAS Heng Liu, Li Ding, Jing Jin, Jianjun Zhou
2018	J	`jnl`	A low-cost digital-domain foreground calibration for high resolution SAR ADCs. Microelectron. J. Rui Guan, Jing Jin, Jianjun Zhou
2017	—	`conf`	A high-speed low-power charge pump with dynamic current matching. ASICON Licheng Xu, Xinchi Gao, Jing Jin
2017	—	`conf`	A passive mixer-first receiver with negative feedback for impedance matching. ASICON Shaoqin Yao, LiTong Liu, Jing Jin
2017	—	`conf`	A wideband simplified transformer-based VCO with digital amplitude calibration. MWSCAS Xinchi Gao, Licheng Xu, Jing Jin, Naifeng Jing, Jianjun Zhou
2016	J	`jnl`	Analysis of Input LCR Matched N-Path Filter. IEEE Trans. Circuits Syst. I Regul. Pap. Zhijian Lu, Jing Jin, Tingting Mo, Jianjun Zhou
2016	J	`jnl`	Wideband dual-mode complementary metal-oxide-semiconductor receiver. IET Circuits Devices Syst. Rui Guan, Jing Jin, Wenjie Pan, Dongpo Chen, Jianjun Zhou
2015	—	`conf`	A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunability. ASICON Bukun Pan, Jing Jin, Jianjun Zhou
2014	C	`conf`	Digital spur calibration of multi-modulus fractional frequency LO divider utilizing most correlated comparison algorithm. ISCAS Jing Jin, Bukun Pan, Xiaoming Liu, Jianjun Zhou
2014	C	`conf`	Injection-Locking Frequency Divider based dual-modulus prescalers with extended locking range. ISCAS Jing Jin, Bukun Pan, Xiaoming Liu, Jianjun Zhou
2012	C	`conf`	Anti-interference pseudo-differential wideband LNA for DVB-S.2 RF tuners. ISCAS Hui Wang, Wufeng Wang, Jing Jin, Dongpo Chen, Jianjun Zhou
2012	J	`jnl`	Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider. IEEE Trans. Circuits Syst. I Regul. Pap. Jing Jin, Xiaoming Liu, Tingting Mo, Jianjun Zhou
2011	C	`conf`	Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs. ISCAS Xiaoming Liu, Jing Jin, Xi Li, Jianjun Zhou
2011	C	`conf`	Linear range extensible Phase Frequency Detector and Charge Pump for fast frequency acquisition. ISCAS Xiaoming Liu, Jing Jin, Cui Mao, Jianjun Zhou