Jing Guo

20 papers Journal 16Unranked 4
YearRankTypeTitle / Venue / Authors
2022 — conf
A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset Tolerance.
DFT
Shanshan Liu, Jing Guo, Xiaochen Tang, Pedro Reviriego, Fabrizio Lombardi
2021 J jnl
Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design.
IEEE Trans. Emerg. Top. Comput.
Shanshan Liu, Pedro Reviriego, Jing Guo, Jie Han, Fabrizio Lombardi
2021 J jnl
High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets.
IEEE Trans. Aerosp. Electron. Syst.
Jing Guo, Shanshan Liu, Xiaohui Su, Chunhua Qi, Fabrizio Lombardi
2021 J jnl
Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS.
IEEE Trans. Emerg. Top. Comput.
Aibin Yan, Chaoping Lai, Yinlei Zhang, Jie Cui, Zhengfeng Huang, Jie Song, Jing Guo, Xiaoqing Wen
2020 J jnl
Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jing Guo, Shanshan Liu, Lei Zhu, Fabrizio Lombardi
2020 J jnl
Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology.
IEEE Access
Nan Zhang, Xiaohui Su, Jing Guo
2020 J jnl
Self-Recovery Tolerance Latch Design Based on the Radiation Mechanism.
IEEE Access
Qiang Li, Xiaohui Su, Jing Guo, Chunhua Qi
2019 J jnl
A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Guo, Shanshan Liu, Lei Zhu, Fabrizio Lombardi
2019 J jnl
Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout.
IEEE Trans. Reliab.
Aibin Yan, Zhen Wu, Jing Guo, Jie Song, Xiaoqing Wen
2018 J jnl
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Guo, Lei Zhu, Yu Sun, Huiliang Cao, Hai Huang, Tianqi Wang, Chunhua Qi, Rongsheng Zhang, Xuebing Cao, Liyi Xiao, Zhigang Mao
2018 — conf
Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique.
ITC-Asia
Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo
2017 J jnl
A Cost-Effective Relative Humidity Sensor Based on Side Coupling Induction Technology.
Sensors
Yingzi Zhang, Yulong Hou, Wenyi Liu, Huixin Zhang, Yanjun Zhang, Zhidong Zhang, Jing Guo, Jia Liu, Liang Zhang, Qiu-lin Tan
2017 J jnl
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Guo, Lei Zhu, Wenyi Liu, Hai Huang, Shanshan Liu, Tianqi Wang, Liyi Xiao, Zhigang Mao
2015 — conf
Fault Secure Encoder and Decoder Designs for Matrix Codes.
CAD/Graphics
Shanshan Liu, Liyi Xiao, Jing Guo, Zhigang Mao
2015 — conf
Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories.
ISQED
Liyi Xiao, Jiaqiang Li, Jie Li, Jing Guo
2015 J jnl
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology.
Microelectron. Reliab.
Chunhua Qi, Liyi Xiao, Jing Guo, Tianqi Wang
2015 J jnl
Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology.
IEEE Trans. Reliab.
Jing Guo, Liyi Xiao, Tianqi Wang, Shanshan Liu, Xu Wang, Zhigang Mao
2014 J jnl
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao
2014 J jnl
Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jing Guo, Liyi Xiao, Zhigang Mao
2013 J jnl
Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs.
IEEE Micro
Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao