Jing-Yang Jou

128 papers A* 3A 12C 9Misc 1Journal 44Unranked 59
YearRankTypeTitle / Venue / Authors
2024 — conf
Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability.
SOCC
Yu-Guang Chen, Yi-Chen Ho, Jing-Yang Jou
2024 — conf
TNSS: Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks.
APCCAS
Yun-Yin Huang, Yu-Guang Chen, Jing-Yang Jou
2023 C conf
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis.
VLSI-SoC
Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang
2022 — conf
A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design.
AICAS
Yu-Guang Chen, Tsung-Han Hsieh, Yi-Chen Ho, Jing-Yang Jou
2021 — conf
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method.
ASP-DAC
Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou
2021 — conf
A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks.
SoCC
Yu-Guang Chen, Chi-Wei Hsu, Hung-Yi Chiang, Tsung-Han Hsieh, Jing-Yang Jou
2021 — conf
A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions.
ISOCC
Yu-Guang Chen, Hung-Yi Chiang, Chi-Wei Hsu, Tsung-Han Hsieh, Jing-Yang Jou
2021 A conf
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design.
DATE
Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou
2016 — conf
Chain-based pin count minimization for general-purpose digital microfluidic biochips.
ASP-DAC
Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou
2016 A conf
Resource-aware functional ECO patch generation.
DATE
An-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou
2016 C conf
Wave digital filter based analog circuit emulation on FPGA.
ISCAS
Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He
2015 J jnl
A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs.
IEEE Trans. Computers
Bo-Cheng Charles Lai, Hsien-Kai Kuo, Jing-Yang Jou
2015 J jnl
Power-Efficient Instancy Aware DRAM Scheduling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Gung-Yu Pan, Chih-Yen Lai, Jing-Yang Jou, Bo-Cheng Charles Lai
2015 J jnl
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors.
ACM Trans. Embed. Comput. Syst.
Gung-Yu Pan, Jed Yang, Jing-Yang Jou, Bo-Cheng Charles Lai
2014 A conf
A learning-on-cloud power management policy for smart devices.
ICCAD
Gung-Yu Pan, Bo-Cheng Charles Lai, Sheng-Yen Chen, Jing-Yang Jou
2014 — conf
A read-write aware DRAM scheduling for power reduction in multi-core systems.
ASP-DAC
Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo, Jing-Yang Jou
2014 J jnl
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog.
ACM Trans. Design Autom. Electr. Syst.
An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou
2014 J jnl
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bu-Ching Lin, Juinn-Dar Huang, Jing-Yang Jou
2014 J jnl
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors.
J. Inf. Sci. Eng.
Bu-Ching Lin, Ming-En Shih, Juinn-Dar Huang, Jing-Yang Jou
2014 J jnl
Reducing Contention in Shared Last-Level Cache for Throughput Processors.
ACM Trans. Design Autom. Electr. Syst.
Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou
2014 J jnl
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors.
ACM Trans. Design Autom. Electr. Syst.
Gung-Yu Pan, Jing-Yang Jou, Bo-Cheng Lai
2013 — conf
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs.
ASP-DAC
Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou
2012 — conf
A formal method to improve SystemVerilog functional coverage.
HLDVT
An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou
2012 J jnl
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou
2012 — conf
Thread affinity mapping for irregular data access on shared Cache GPGPU.
ASP-DAC
Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou
2011 A conf
Design-for-debug layout adjustment for FIB probing and circuit editing.
ITC
Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen
2011 — conf
Equivalence checking of scheduling with speculative code transformations in high-level synthesis.
ASP-DAC
Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
2011 — conf
Mixed non-rectangular block packing for non-Manhattan layout architectures.
ISQED
Meng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou
2010 — conf
Expandable MDC-based FFT architecture and its generator for high-performance applications.
SoCC
Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou
2010 J jnl
FSM-Based Formal Compliance Verification of Interface Protocols.
J. Inf. Sci. Eng.
Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou
2010 — conf
Unleash the parallelism of 3DIC partitioning on GPGPU.
SoCC
Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou
2009 J jnl
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
2009 J jnl
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM.
IEEE Trans. Very Large Scale Integr. Syst.
Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
2009 Misc conf
Multiple-Fault Diagnosis Using Faulty-Region Identification.
VTS
Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu
2009 J jnl
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning.
ACM Trans. Design Autom. Electr. Syst.
Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou
2008 — conf
Crosstalk-avoidance coding for low-power on-chip bus.
ICECS
Kuang-Chin Cheng, Jing-Yang Jou
2008 J jnl
Verification of Pin-Accurate Port Connections.
IEEE Des. Test Comput.
Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou
2007 — conf
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses.
ASP-DAC
Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
2007 J jnl
A Tableless Approach for High-Level Power Modeling Using Neural Networks.
J. Inf. Sci. Eng.
Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou
2007 J jnl
Hybrid Wordlength Optimization Methods of Pipelined FFT Processors.
IEEE Trans. Computers
Cheng-Yeh Wang, Chih-Bin Kuo, Jing-Yang Jou
2007 J jnl
Observability Analysis on HDL Descriptions for Effective Functional Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
2006 — conf
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication.
ASP-DAC
Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
2006 J jnl
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging.
IEEE Trans. Computers
Chia-Chih Yen, Jing-Yang Jou
2006 — conf
FSM-based transaction-level functional coverage for interface compliance verification.
ASP-DAC
Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
2006 — conf
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
SoCC
Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou
2006 J jnl
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou
2006 J jnl
Reliable crosstalk-driven interconnect optimization.
ACM Trans. Design Autom. Electr. Syst.
Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
2005 J jnl
An efficient heterogeneous tree multiplexer synthesis technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
2005 — conf
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness.
ASP-DAC
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
2005 — conf
An optimum algorithm for compacting error traces for efficient functional debugging.
HLDVT
Chia-Chih Yen, Jing-Yang Jou
2005 — conf
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip.
ASP-DAC
Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou
2005 — conf
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs.
ISCAS (6)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
2005 — conf
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.
ISCAS (4)
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
2005 — conf
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model.
HLDVT
Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
2004 J jnl
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation.
IEEE Des. Test Comput.
Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen
2004 — conf
An efficient approach for hierarchical submodule extraction.
ISCAS (5)
Yi-Wei Lin, Jing-Yang Jou
2004 — conf
An efficient logic extraction algorithm using partitioning and circuit encoding.
ISCAS (5)
Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang
2004 — conf
Enhancing sequential depth computation with a branch-and-bound algorithm.
HLDVT
Chia-Chih Yen, Jing-Yang Jou
2004 C conf
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs.
ICCD
Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou
2004 — conf
Layout techniques for on-chip interconnect inductance reduction.
ASP-DAC
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
2004 — conf
On compliance test of on-chip bus for SOC.
ASP-DAC
Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou
2004 — conf
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming.
ASP-DAC
Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
2004 — conf
RLC effects on worst-case switching pattern for on-chip buses.
ISCAS (2)
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
2004 J jnl
Simultaneous floor plan and buffer-block optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
2004 A conf
Verification on Port Connections.
ITC
Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang
2003 J jnl
A Design-for-Verification Technique for Functional Pattern Reduction.
IEEE Des. Test Comput.
Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
2003 J jnl
An Efficient Power Model for IP-Level Complex Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou
2003 — conf
An automatic interconnection rectification technique for SoC design integration.
ASP-DAC
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2003 — conf
An efficient IP-level power model for complex digital circuits.
ASP-DAC
Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou
2003 — conf
An efficient approach for error diagnosis in HDL design.
ISCAS (4)
Che-Hua Shih, Jing-Yang Jou
2003 J jnl
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2003 — conf
Simultaneous floorplanning and buffer block planning.
ASP-DAC
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
2003 — conf
SoC design integration by using automatic interconnection rectification.
ISCAS (4)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2002 — conf
A Practical Approach to Cycle Bound Estimation for Property Checking.
IWLS
Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou
2002 J jnl
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2002 J jnl
Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation.
J. Circuits Syst. Comput.
Heng-Liang Huang, Jing-Yang Jou
2002 — conf
Effective Error Diagnosis for RTL Designs in HDLs.
Asian Test Symposium
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
2002 J jnl
On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
An AVPG for SOC design verification with port order fault model.
ISCAS (5)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Asian Test Symposium
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
An efficient design-for-verification technique for HDLs.
ASP-DAC
Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
2001 — conf
Automatic Functional Vector Generation Using the Interacting FSM Model.
ISQED
Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou
2001 J jnl
Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou
2001 — conf
Grouped input power sensitive transition an input sequence compaction technique for power estimation.
ISCAS (5)
Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen
2001 — conf
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model.
HLDVT
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
On placement and routing of wafer scale memory.
ICECS
Li-An Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu, Tai-Sheng Feng
2001 — conf
On tri-state buffer inference in HDL synthesis.
ISCAS (5)
Hen-Ming Lin, Jing-Yang Jou
2001 J jnl
Unified functional decomposition via encoding for FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst.
Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
2000 — conf
A new method for constructing IP level power model based on power sensitivity.
ASP-DAC
Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
2000 C conf
A novel approach for functional coverage measurement in HDL.
ISCAS
Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, Hsing-Ming Juan
2000 J jnl
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst.
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
2000 J jnl
An Automatic Controller Extractor for HDL Descriptions at the RTL.
IEEE Des. Test Comput.
Chien-Nan Jimmy Liu, Jing-Yang Jou
2000 — conf
Collaboration between Industry and Academia in Test Research.
Asian Test Symposium
Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
2000 J jnl
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou
2000 J jnl
On computing the minimum feedback vertex set of a directed graph bycontraction operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hen-Ming Lin, Jing-Yang Jou
2000 — conf
Optimal reliable crosstalk-driven interconnect optimization.
ISPD
Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
1999 J jnl
A structure-oriented power modeling technique for macrocells.
IEEE Trans. Very Large Scale Integr. Syst.
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
1999 C conf
An Efficient Functional Coverage Test for HDL Descriptions at RTL.
ICCD
Chien-Nan Jimmy Liu, Jing-Yang Jou
1999 C conf
Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD.
ICCD
Hen-Ming Lin, Jing-Yang Jou
1999 — conf
Hierarchical Floorplan Design on the Internet.
ASP-DAC
Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang
1999 A* conf
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.
DAC
Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
1999 J jnl
Two-level logic minimization for low power.
ACM Trans. Design Autom. Electr. Syst.
Jyh-Mou Tseng, Jing-Yang Jou
1998 J jnl
A Logical Fault Model for Library Coherence Checking.
J. Inf. Sci. Eng.
Shing-Wu Tung, Jing-Yang Jou
1998 A* conf
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.
DAC
Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
1998 J jnl
On circuit clustering for area/delay tradeoff under capacity and pin constraints.
IEEE Trans. Very Large Scale Integr. Syst.
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
1998 — conf
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model.
Asian Test Symposium
Shing-Wu Tung, Jing-Yang Jou
1997 — conf
A power driven two-level logic optimizer.
ASP-DAC
Jyh-Mou Tseng, Jing-Yang Jou
1997 A conf
A power modeling and characterization method for macrocells using structure information.
ICCAD
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
1997 — conf
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture.
ASP-DAC
Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei
1997 J jnl
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo
1997 C conf
Power Driven Partial Scan.
ICCD
Jing-Yang Jou, Ming-Chang Nien
1996 A conf
A power modeling and characterization method for the CMOS standard cell library.
ICCAD
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
1996 — conf
An Efficient PRPG Strategy By Utilizing Essential Faults.
Asian Test Symposium
Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo
1996 A conf
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
ICCAD
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
1996 — conf
Easily Testable Data Path Allocation Using Input/Output Registers.
Asian Test Symposium
Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao
1995 — conf
An effective BIST design for PLA.
Asian Test Symposium
Jing-Yang Jou
1995 A conf
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
ICCAD
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
1995 J jnl
Timing-Driven Partial Scan.
IEEE Des. Test Comput.
Jing-Yang Jou, Kwang-Ting (Tim) Cheng
1992 J jnl
A functional fault model for sequential machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kwang-Ting Cheng, Jing-Yang Jou
1991 A conf
Timing-Driven Partial Scan.
ICCAD
Jing-Yang Jou, Kwang-Ting Cheng
1990 A conf
A Single-State-Transition Fault Model for Sequential Machines.
ICCAD
Kwang-Ting Cheng, Jing-Yang Jou
1990 A conf
Functional test generation for finite state machines.
ITC
Kwang-Ting Cheng, Jing-Yang Jou
1989 C conf
OPAM: an efficient output phase assignment for multilevel logic minimization.
ICCD
Chin-Long Wey, Sin-Min Chang, Jing-Yang Jou
1988 C conf
A testable PLA design with low overhead and ease of test generation.
ICCD
Jing-Yang Jou
1988 A* conf
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping.
DAC
Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou
1988 — conf
Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing.
ICPP (1)
Jing-Yang Jou, Jacob A. Abraham
1988 J jnl
Fault-Tolerant FFT Networks.
IEEE Trans. Computers
Jing-Yang Jou, Jacob A. Abraham
1986 J jnl
Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures.
Proc. IEEE
Jing-Yang Jou, Jacob A. Abraham