Jing-Reng Huang

16 papers A 2Misc 2Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2007 J jnl
STEAC: A Platform for Automatic SOC Test Integration.
IEEE Trans. Very Large Scale Integr. Syst.
Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
2004 J jnl
A Built-In Parametric Timing Measurement Unit.
IEEE Des. Test Comput.
Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang
2004 A conf
An SOC Test Integration Platform and Its Industrial Realization.
ITC
Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
2002 — conf
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.
DFT
Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang
2002 — conf
Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
Asian Test Symposium
Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2002 — conf
Test Scheduling of BISTed Memory Cores for SOC.
Asian Test Symposium
Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2001 Misc conf
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs.
VTS
Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng
2001 A conf
A built-in timing parametric measurement unit.
ITC
Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
2001 — conf
A low-cost CMOS time interval measurement core.
ISCAS (4)
Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
2001 — conf
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
Asian Test Symposium
Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2001 Misc conf
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses.
VTS
Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng
2000 — conf
A programmable built-in self-test core for embedded memories.
ASP-DAC
Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
2000 — conf
A realistic fault model for flash memories.
Asian Test Symposium
Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang
2000 — conf
An FPGA-based re-configurable functional tester for memory chips.
Asian Test Symposium
Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu
2000 — conf
BRAINS: A BIST Compiler for Embedded Memories.
DFT
Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai
1999 J jnl
A Programmable BIST Core for Embedded DRAM.
IEEE Des. Test Comput.
Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang