Jing-Jia Liou - RankMe

74 papers A* 6A 15C 3Misc 4Journal 9Unranked 37

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis. ITC Chien-Hsing Liang, Yu-Hong Chao, Jing-Jia Liou, Harry H. Chen
2025	—	`conf`	An Adaptive Scheme of Threshold Adjustment for Dynamic Sparsity Extraction of Self-Attention Network. AICAS Yong-Lun Xiao, Chia-Wei Chang, Cheng-Ting Shih, Jing-Jia Liou, Chih-Tsun Huang, Yao-Hua Chen, Juin-Ming Lu
2025	—	`conf`	Fault Injection and Tolerance Analysis of Battery Management Systems Using SystemC-AMS. ITC-Asia Hao-Yang Chi, Chih-Tsun Huang, Jing-Jia Liou, Harry H. Chen
2025	A	`conf`	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis. ITC Quan Cheng, Hao-Yang Chi, Chien-Hsing Liang, Yu-Hong Chao, Huizi Zhang, Yuan Liang, Mingtao Zhang, Wang Liao, Jinjun Xiong, Jing-Jia Liou, Masanori Hashimoto, Longyang Lin
2025	A	`conf`	Tenpura: A General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-fast Reliability Analysis. ICCAD Quan Cheng, Huizi Zhang, Chien-Hsing Liang, Mingtao Zhang, Jing-Jia Liou, Jinjun Xiong, Longyang Lin, Masanori Hashimoto
2025	A	`conf`	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks. ITC Po-Sheng Chiu, Chih-Yu Hsu, Chih-Tsun Huang, Jing-Jia Liou
2025	—	`conf`	Transformer-Based Architecture for Fault Propagation Modeling in Transient Fault Analysis. ATS Chia-Ying Lin, Jing-Jia Liou, Harry Chen
2023	—	`conf`	HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration. SOCC Jyun-Siou Huang, Ting-Han Chou, Juin-Ming Lu, Chih-Tsun Huang, Jing-Jia Liou
2023	C	`conf`	MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy. ICCD Chia-Wei Chang, Jing-Jia Liou, Chih-Tsun Huang, Wei-Chung Hsu, Juin-Ming Lu
2023	—	`conf`	Signal Reduction of Signature Blocks for Transient Fault Debugging. ATS Chun-Yeh Wang, Chien-Hsing Liang, Jing-Jia Liou, Harry H. Chen
2022	—	`conf`	Efficient Segment-wise Pruning for DCNN Inference Accelerators. VLSI-DAT Che-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu
2022	—	`conf`	FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis. ATS Zih-Ming Huang, Dun-An Yang, Jing-Jia Liou, Harry H. Chen
2022	—	`conf`	Fast DNN-based Mechatronics Prototyping Platform on Robotic Arm Control. AICAS Yu-Chien Chung, Hao-Hsiang Lian, Yong-Lun Xiao, Chih-Tsun Huang, Jing-Jia Liou
2022	—	`conf`	Foreword: ATS 2022. ATS Jin-Fu Li, Jing-Jia Liou
2022	A	`conf`	Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging. ITC Dun-An Yang, Jing-Jia Liou, Harry H. Chen
2021	A	`conf`	ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph. ITC Dun-An Yang, Yu-Teng Chang, Ting-Shuo Hsu, Jing-Jia Liou, Harry H. Chen
2021	—	`conf`	Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study. ATS Dun-An Yang, Jing-Jia Liou, Harry H. Chen
2021	—	`conf`	Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks. AICAS Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, Tzu-yu Chen, Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu
2020	—	`conf`	An ISA-level Accurate Fault Simulator for System-level Fault Analysis. ATS Jiang-Tang Xiao, Ting-Shuo Hsu, Christian M. Fuchs, Yu-Teng Chang, Jing-Jia Liou, Harry H. Chen
2019	A	`conf`	A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis. FPGA Chia-Wei Chang, Zi-Qi Zhong, Jing-Jia Liou
2019	—	`conf`	NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators. VLSI-DAT Yi-Che Lee, Ting-Shuo Hsu, Chun-Tse Chen, Jing-Jia Liou, Juin-Ming Lu
2017	—	`conf`	Design space exploration with a cycle-accurate systemC/TLM DRAM controller model. VLSI-DAT Ting-Shuo Hsu, Chao-Chieh Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu
2017	—	`conf`	Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. VLSI-DAT Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu
2017	—	`conf`	Post-Silicon Test Flow for Aging Prediction. ATS Zih-Huan Gao, Hau Hsu, Ting-Shuo Hsu, Jing-Jia Liou
2015	—	`conf`	A fast and accurate network-on-chip timing simulator with a flit propagation model. ASP-DAC Ting-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, Jing-Jia Liou
2015	C	`conf`	Cost reduction of system-level tests with stressed structural tests and SVM. VLSI-SoC Jing-Jia Liou, Meng-Ta Hsieh, Jun-Fei Cherng, Harry H. Chen
2015	—	`conf`	Design of a scalable many-core processor for embedded applications. ASP-DAC Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou
2015	J	`jnl`	Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment. IEEE Trans. Multim. Tsun-Hsien Wang, Cheng-Wen Chiu, Wei-Chen Wu, Jen-Wen Wang, Chun-Yi Lin, Ching-Te Chiu, Jing-Jia Liou
2014	C	`conf`	Chip clustering with mutual information on multiple clock tests and its application to yield tuning. ICCD Jiun-Yi Chiang, Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou
2014	—	`conf`	Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu
2013	—	`conf`	A Region-Based Framework for Design Feature Identification of Systematic Process Variations. Asian Test Symposium Shuo-You Hsu, Chih-Hsiang Hsu, Ting-Shuo Hsu, Jing-Jia Liou
2013	J	`jnl`	AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
2013	—	`conf`	Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures. MES Jyu-Yuan Lai, Ting-Shuo Hsu, Po-Yu Chen, Chih-Tsun Huang, Yu-Hsun Chen, Jing-Jia Liou
2012	—	`conf`	Design and analysis of a many-core processor architecture for multimedia applications. APSIPA Jyu-Yuan Lai, Po-Yu Chen, Ting-Shuo Hsu, Chih-Tsun Huang, Jing-Jia Liou
2012	—	`conf`	On error modeling of electrical bugs for post-silicon timing validation. ASP-DAC Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing-Jia Liou
2012	—	`conf`	Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data. Asian Test Symposium Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou
2011	A*	`conf`	A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
2011	—	`conf`	Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs. ASP-DAC Jing-Jia Liou, Ying-Yen Chen, Chun-Chia Chen, Chung-Yen Chien, Kuo-Li Wu
2011	J	`jnl`	Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. J. Circuits Syst. Comput. Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin
2011	—	`conf`	TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler. ASP-DAC Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung
2010	—	`conf`	AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
2010	J	`jnl`	Automatic Test Wrapper Synthesis for a Wireless ATE Platform. IEEE Des. Test Comput. Chun-Yu Yang, Ying-Yen Chen, Sung-Yu Chen, Jing-Jia Liou
2009	—	`conf`	A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities. Asian Test Symposium Ying-Yen Chen, Jing-Jia Liou
2009	—	`conf`	Multiple-Core under Test Architecture for HOY Wireless Testing Platform. Asian Test Symposium Sung-Yu Chen, Ying-Yen Chen, Chun-Yu Yang, Jing-Jia Liou
2008	—	`conf`	Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. ATS Chun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
2008	J	`jnl`	Diagnosis Framework for Locating Failed Segments of Path Delay Faults. IEEE Trans. Very Large Scale Integr. Syst. Ying-Yen Chen, Jing-Jia Liou
2008	—	`conf`	High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths. ATS Ming-Ting Hsieh, Shun-Yen Lu, Jing-Jia Liou, Augusli Kifli
2007	—	`conf`	A prototype of a wireless-based test system. SoCC Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang
2007	A	`conf`	An efficient SAT-based path delay fault ATPG with an unified sensitization model. ITC Shun-Yen Lu, Ming-Ting Hsieh, Jing-Jia Liou
2007	J	`jnl`	BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. IET Comput. Digit. Tech. Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang
2007	A*	`conf`	Extraction of Statistical Timing Profiles Using Test Data. DAC Ying-Yen Chen, Jing-Jia Liou
2007	Misc	`conf`	Handling Pattern-Dependent Delay Faults in Diagnosis. VTS Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou
2006	—	`conf`	Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method. DFT Ying-Yen Chen, Jing-Jia Liou
2006	A	`conf`	Exploring linear structures of critical path delay faults to reduce test efforts. ICCAD Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou
2005	Misc	`conf`	A BIST Scheme for FPGA Interconnect Delay Faults. VTS Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
2005	A	`conf`	Diagnosis framework for locating failed segments of path delay faults. ITC Ying-Yen Chen, Min-Pin Kuo, Jing-Jia Liou
2004	—	`conf`	An Application-Independent Delay Testing Methodology for Island-Style FPGA. DFT Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
2004	J	`jnl`	Critical path selection for delay fault testing based upon a statistical timing model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng
2003	J	`jnl`	Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting (Tim) Cheng
2003	A	`conf`	Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
2003	Misc	`conf`	Diagnosis of Delay Defects Using Statistical Timing Models. VTS Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou
2003	A*	`conf`	Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
2003	—	`conf`	Experience in critical path selection for deep sub-micron delay test and timing validation. ASP-DAC Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng
2003	J	`jnl`	Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
2003	—	`conf`	On Structural vs. Functional Testing for Delay Faults. ISQED Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang
2002	A	`conf`	Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
2002	A*	`conf`	Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
2002	A*	`conf`	False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. DAC Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
2002	A	`conf`	On theoretical and practical considerations of path selection for delay fault testing. ICCAD Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng
2001	A	`conf`	Delay testing considering crosstalk-induced effects. ITC Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
2001	A*	`conf`	Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
2000	A	`conf`	Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. ICCAD Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
2000	Misc	`conf`	Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. VTS Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee
2000	—	`conf`	Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu