Jin Yang

48 papers A* 9A 3B 5C 5Journal 14Unranked 12
YearRankTypeTitle / Venue / Authors
2025 — conf
Formal Verification of a Custom Compiler for a Fully Homomorphic Encryption Accelerator.
ISQED
Zhenkun Yang, Suvadeep Banerjee, Jeremy Casas, Jin Yang
2024 J jnl
A Systematic Translation Validation Framework for MLIR-Based Compilers.
Int. J. Softw. Eng. Knowl. Eng.
Yanzhao Wang, Fei Xie, Zhenkun Yang, Pasquale Cocchini, Jin Yang
2024 J jnl
Correct-by-Construction Design of Custom Accelerator Microarchitectures.
IEEE Trans. Computers
Jin Yang, Zhenkun Yang, Jeremy Casas, Sandip Ray
2023 A conf
An Automated Verification Framework for HalideIR-Based Compiler Transformations.
DATE
Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang
2023 — conf
An Equivalence Checking Framework for Agile Hardware Design.
ASP-DAC
Yanzhao Wang, Fei Xie, Zhenkun Yang, Pasquale Cocchini, Jin Yang
2023 — conf
High-level Synthesis for Domain Specific Computing.
ISPD
Hanchen Ye, HyeGang Jun, Jin Yang, Deming Chen
2023 A* conf
Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design.
DAC
Jin Yang, Jeremy Casas, Zhenkun Yang
2023 J jnl
Towards A Correct-by-Construction FHE Model.
IACR Cryptol. ePrint Arch.
Zhenkun Yang, Wen Wang, Jeremy Casas, Pasquale Cocchini, Jin Yang
2023 A* conf
Towards A Formally Verified Fully Homomorphic Encryption Compute Engine.
DAC
Jeremy Casas, Zhenkun Yang, Wen Wang, Jin Yang, Adwait Godbole
2022 A* conf
Accelerator design with decoupled hardware customizations: benefits and challenges: invited.
DAC
Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang
2022 J jnl
Mining Patterns From Concurrent Execution Traces.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2021 — conf
A Comparative Study of Specification Mining Methods for SoC Communication Traces.
ISVLSI
Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2021 J jnl
A Hertzian contact based model to estimate thermal resistance of thermal interface material for high-performance microprocessors.
Microelectron. J.
David Shia, Jin Yang
2021 J jnl
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration.
CoRR
Suvadeep Banerjee, Steve Burns, Pasquale Cocchini, Abhijit Davare, Shweta Jain, Desmond Kirkpatrick, Anton Sorokin, Jin Yang, Zhenkun Yang
2021 — conf
Mining Message Flows from System-on-Chip Execution Traces.
ISQED
Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2021 C conf
Model Synthesis for Communication Traces of System Designs.
ICCD
Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2021 J jnl
Model Synthesis for Communication Traces of System-on-Chip Designs.
CoRR
Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2020 J jnl
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.
CoRR
Yuting Cao, Hao Zheng, Sandip Ray, Jin Yang
2020 J jnl
Mining Message Flows from System-on-Chip Execution Traces.
CoRR
Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
2020 — conf
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs.
ISQED
Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng
2020 J jnl
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs.
CoRR
Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng
2020 A* conf
UEFI Firmware Fuzzing with Simics Virtual Platform.
DAC
Zhenkun Yang, Yuriy Viktorov, Jin Yang, Jiewen Yao, Vincent Zimmer
2017 C conf
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.
ICCD
Yuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang
2016 — conf
Protocol-guided analysis of post-silicon traces under limited observability.
ISQED
Hao Zheng, Yuting Cao, Sandip Ray, Jin Yang
2015 A* conf
Correctness and security at odds: post-silicon validation of modern SoC designs.
DAC
Sandip Ray, Jin Yang, Abhishek Basak, Swarup Bhunia
2014 C conf
From visual to logical formalisms for SoC validation.
MEMOCODE
Ranan Fraer, Doron Keren, Zurab Khasidashvili, Alexander Novakovsky, Avi Puder, Eli Singerman, Eran Talmor, Moshe Y. Vardi, Jin Yang
2014 — conf
Security of SoC firmware load protocols.
HOST
Sava Krstic, Jin Yang, David W. Palmer, Randy B. Osborne, Eran Talmor
2012 J jnl
Formal-Analysis-Based Trace Computation for Post-Silicon Debug.
IEEE Trans. Very Large Scale Integr. Syst.
Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang
2012 J jnl
SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience.
IEEE Des. Test Comput.
Doron Bustan, Dmitry Korchemny, Erik Seligman, Jin Yang
2010 A conf
Optimizing equivalence checking for behavioral synthesis.
DATE
Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang
2009 B conf
Formal Verification for High-Assurance Behavioral Synthesis.
ATVA
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Yang
2008 B conf
BackSpace: Formal Analysis for Post-Silicon Debug.
FMCAD
Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang
2008 A* conf
Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation.
DAC
Yan Chen, Fei Xie, Jin Yang
2007 B conf
Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation.
FMCAD
Yan Chen, Yujing He, Fei Xie, Jin Yang
2006 C conf
Maximal Models of Assertion Graph in GSTE.
TAMC
Guowu Yang, Jin Yang, Xiaoyu Song, Fei Xie
2006 J jnl
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski
2006 B conf
Verification Challenges and Opportunities in the New Era of Microprocessor Design.
ATVA
Jin Yang
2005 — conf
Implication of assertion graphs in GSTE.
ASP-DAC
Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song
2005 — conf
Partitioned model checking from software specifications.
ASP-DAC
Xiushan Feng, Alan J. Hu, Jin Yang
2005 — conf
Tightly integrate dynamic verification with formal verification: a GSTE based approach.
ASP-DAC
Jin Yang, Avi Puder
2004 A* conf
Compositional Specification and Model Checking in GSTE.
CAV
Jin Yang, Carl-Johan H. Seger
2004 A* conf
Quantum logic synthesis by symbolic reachability analysis.
DAC
William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski
2003 J jnl
Introduction to generalized symbolic trajectory evaluation.
IEEE Trans. Very Large Scale Integr. Syst.
Jin Yang, Carl-Johan H. Seger
2003 — conf
Reasoning about GSTE Assertion Graphs.
CHARME
Alan J. Hu, Jeremy Casas, Jin Yang
2002 A conf
GSTE through a case study.
ICCAD
Jin Yang, Amit Goel
2002 B conf
Generalized Symbolic Trajectory Evaluation - Abstraction in Action.
FMCAD
Jin Yang, Carl-Johan H. Seger
2001 C conf
Introduction to Generalized Symbolic Trajectory Evaluation.
ICCD
Jin Yang, Carl-Johan H. Seger
2000 A* conf
Lazy symbolic model checking.
DAC
Jin Yang, Andreas Tiemeyer