Jin-Tai Yan

118 papers A* 1A 2C 19Misc 4Journal 42Unranked 50
YearRankTypeTitle / Venue / Authors
2026 J jnl
Layer-Constrained GNR Area Routing With CNT-Via Insertion for Via Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan, Chia-Heng Yen
2024 J jnl
Delay-Constrained GNR Routing With CNT-Via Insertion in Nano-Scale Designs.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jin-Tai Yan
2024 J jnl
Design and analysis of sum-prediction adder.
Integr.
Chia-Heng Yen, Jin-Tai Yan
2023 — conf
Layer-Minimization-Oriented GNR Area Routing.
ICECS
Chia-Heng Yen, Jin-Tai Yan
2022 J jnl
Bus Assignment Considering Flexible Escape Routing for Layer Minimization in PCB Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
2022 J jnl
Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Tai Yan
2022 J jnl
Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
2021 — conf
Efficient Standard-Cell Legalization for Minimization of Total Movement.
ICECS
Jin-Tai Yan, Po-Yuan Huang, Chia-Hsun Yen
2021 J jnl
Fuzzy-Clustering-Based Circular Topological Via Minimization in PCB Designs.
IEEE Trans. Fuzzy Syst.
Jin-Tai Yan
2021 J jnl
Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
2021 J jnl
Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Tai Yan
2021 J jnl
Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Tai Yan
2020 C conf
Construction of Obstacle-Avoiding Delay-Driven GNR Routing Tree.
TENCON
Jin-Tai Yan, Po-Yuan Huang, Chien-Yi Wang
2020 J jnl
Delay-Constrained GNR Routing for Layer Minimization.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Tai Yan
2020 J jnl
Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Tai Yan
2020 J jnl
Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment.
ACM Trans. Design Autom. Electr. Syst.
Jin-Tai Yan
2019 — conf
Construction of Delay-Driven GNR Routing Tree.
NEWCAS
Jin-Tai Yan, Chia-Heng Yen
2019 J jnl
Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
2019 J jnl
Single-Layer GNR Routing for Minimization of Bending Delay.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
2019 J jnl
Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing.
ACM Trans. Design Autom. Electr. Syst.
Jin-Tai Yan
2018 J jnl
Direction-Constrained Rectangle Escape Routing.
ACM Trans. Design Autom. Electr. Syst.
Jin-Tai Yan
2018 — conf
Feasible Assignment of Micro-Bumps in 3D ICs.
NEWCAS
Jin-Tai Yan, Chia-Heng Yen
2018 J jnl
On-Chip Optical Channel Routing for Signal Loss Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
2017 J jnl
Layer Assignment of Escape Buses with Consecutive Constraints in PCB Designs.
ACM Trans. Design Autom. Electr. Syst.
Jin-Tai Yan
2017 J jnl
One-Sided Net Untangling With Internal Detours for Bus Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
2016 — conf
Cell-aware MBFF utilization for clock power reduction.
ICECS
Jin-Tai Yan, Meng-Tian Chen, Chia-Heng Yen
2016 J jnl
Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
2016 J jnl
Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs.
ACM Trans. Design Autom. Electr. Syst.
Jin-Tai Yan
2015 J jnl
Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs.
Integr.
Jin-Tai Yan
2015 J jnl
Length-constrained escape routing of differential pairs.
Integr.
Jin-Tai Yan
2015 J jnl
Single-layer obstacle-aware routing for substrate interconnections.
Integr.
Jin-Tai Yan
2014 — conf
Efficient micro-bump assignment for RDL routing in 3DICs.
ICECS
Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen
2014 J jnl
Fault-tolerant analysis of TMR design with noise-aware logic.
Integr.
Jin-Tai Yan
2014 C conf
Feasible region assignment of routing nets in single-layer routing.
ISCAS
Jin-Tai Yan, Yu-Jen Tseng, Chia-Heng Yen
2013 — conf
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
ACM Great Lakes Symposium on VLSI
Jin-Tai Yan, Zhi-Wei Chen
2013 C conf
Post-layout redundant wire insertion for fixing min-delay violations.
ISCAS
Jin-Tai Yan, Zhi-Wei Chen
2013 J jnl
Routability-constrained multi-bit flip-flop construction for clock power reduction.
Integr.
Zhi-Wei Chen, Jin-Tai Yan
2013 — conf
Timing-constrained replacement using spare cells for design changes.
ACM Great Lakes Symposium on VLSI
Zhi-Wei Chen, Jin-Tai Yan
2012 — conf
Density-reduction-oriented layer assignment for rectangle escape routing.
ACM Great Lakes Symposium on VLSI
Jin-Tai Yan, Jun-Min Chung, Zhi-Wei Chen
2012 — conf
Direction-constrained layer assignment for rectangle escape routing.
SoCC
Jin-Tai Yan, Zhi-Wei Chen
2012 C conf
Efficient assignment of inter-die signals for die-stacking SiP design.
ISCAS
Jin-Tai Yan, Chia-Han Kao, Ming-Chien Huang, Zhi-Wei Chen
2012 J jnl
New optimal layer assignment for bus-oriented escape routing.
Integr.
Jin-Tai Yan, Zhi-Wei Chen
2012 C conf
Post-layout OPE-predicted redundant wire insertion for clock skew minimization.
ICCD
Jin-Tai Yan, Zhi-Wei Chen
2012 J jnl
Resource-constrained link insertion for delay reduction.
Integr.
Jin-Tai Yan
2012 — conf
Top-down-based symmetrical buffered clock routing.
ACM Great Lakes Symposium on VLSI
Jin-Tai Yan, Ming-Chien Huang, Zhi-Wei Chen
2012 — conf
Utilization of multi-bit flip-flops for clock power reduction.
ICECS
Zhi-Wei Chen, Jin-Tai Yan
2011 J jnl
IO connection assignment and RDL routing for flip-chip designs.
ACM Trans. Design Autom. Electr. Syst.
Jin-Tai Yan
2011 — conf
New optimal layer assignment for bus-oriented escape routing.
ACM Great Lakes Symposium on VLSI
Jin-Tai Yan, Zhi-Wei Chen
2011 — conf
Obstacle-aware length-matching bus routing.
ISPD
Jin-Tai Yan, Zhi-Wei Chen
2011 A conf
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance.
DATE
Jin-Tai Yan, Zhi-Wei Chen
2011 C conf
Pre-assignment RDL routing via extraction of maximal net sequence.
ICCD
Jin-Tai Yan, Zhi-Wei Chen
2011 — conf
Simultaneous escape routing based on routability-driven net ordering.
SoCC
Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen
2011 A conf
Timing-constrained I/O buffer placement for flip-chip designs.
DATE
Zhi-Wei Chen, Jin-Tai Yan
2010 C conf
Low-cost low-power bypassing-based multiplier design.
ISCAS
Jin-Tai Yan, Zhi-Wei Chen
2010 — conf
Obstacle-aware longest path using rectangular pattern detouring in routing grids.
ASP-DAC
Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen
2010 — conf
Ordered escape routing via routability-driven pin assignment.
ACM Great Lakes Symposium on VLSI
Jin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen
2010 — conf
Resource-constrained timing-driven link insertion for critical delay reduction.
ACM Great Lakes Symposium on VLSI
Jin-Tai Yan, Zhi-Wei Chen
2010 — conf
Routability-driven RDL routing with pin reassignment.
SoCC
Jin-Tai Yan, Ke-Chyuan Chen, Zhi-Wei Chen
2010 C conf
Routability-driven flip-flop merging process for clock power reduction.
ICCD
Zhi-Wei Chen, Jin-Tai Yan
2010 — conf
Routability-driven partitioning-based IO assignment for flip-chip designs.
APCCAS
Jin-Tai Yan, Kai-Ping Lu, Zhi-Wei Chen
2010 — conf
Thermal via planning for temperature reduction in 3D ICs.
SoCC
Jin-Tai Yan, Yu-Cheng Chang, Zhi-Wei Chen
2010 A* conf
Two-sided single-detour untangling for bus routing.
DAC
Jin-Tai Yan, Zhi-Wei Chen
2010 C conf
Width-constrained wire sizing for non-tree interconnections.
ISCAS
Zhi-Wei Chen, Jin-Tai Yan
2009 C conf
Accurate Transformation-based Timing Analysis for RC Non-tree Circuits.
ISCAS
Zhi-Wei Chen, Jin-Tai Yan, Hsing-Lin Ko
2009 — conf
IO connection assignment and RDL routing for flip-chip designs.
ASP-DAC
Jin-Tai Yan, Zhi-Wei Chen
2009 — conf
Low-power multiplier design with row and column bypassing.
SoCC
Jin-Tai Yan, Zhi-Wei Chen
2009 — conf
RDL pre-assignment routing for flip-chip designs.
ACM Great Lakes Symposium on VLSI
Jin-Tai Yan, Zhi-Wei Chen
2009 — conf
Redundant wire insertion for yield improvement.
ACM Great Lakes Symposium on VLSI
Jin-Tai Yan, Zhi-Wei Chen
2008 — conf
Electromigration-aware rectilinear Steiner tree construction for analog circuits.
APCCAS
Jin-Tai Yan, Zhi-Wei Chen
2008 — conf
Flexible escape routing for flip-chip designs.
ICECS
Jin-Tai Yan, Zhi-Wei Chen
2008 — conf
Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids.
ICECS
Jin-Tai Yan, Zhi-Wei Chen
2008 — conf
Thermal-driven white space redistribution for block-level floorplans.
ICECS
Jin-Tai Yan, Zhi-Wei Chen, Yi-Hsiang Chou, Shun-Hua Lin, Herming Chiueh
2008 — conf
Timing-constrained yield-driven redundant via insertion.
APCCAS
Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, Yu-Min Lee
2008 — conf
Timing-driven multi-layer Steiner tree construction with obstacle avoidance.
APCCAS
Jin-Tai Yan, Zhi-Wei Chen
2008 J jnl
Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction.
ACM Trans. Design Autom. Electr. Syst.
Jin-Tai Yan
2007 C conf
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity.
ISCAS
Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu
2007 — conf
Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity.
SoCC
Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu
2007 — conf
Routability-Driven Track Routing for Coupling Capacitance Reduction.
ICECS
Jin-Tai Yan, Zhi-Wei Chen, Kuen-Ming Lin
2007 Misc conf
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization.
VLSI Design
Jin-Tai Yan, Bo-Yi Chiang
2007 — conf
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance.
ICECS
Jin-Tai Yan, Shi-Qin Huang, Zhi-Wei Chen
2006 — conf
Area-Driven White Space Distribution for Detailed Floorplan Design.
ICECS
Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu
2006 Misc conf
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing.
VLSI Design
Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen
2006 C conf
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model.
ISCAS
Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo
2006 C conf
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model.
ISCAS
Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang
2006 — conf
Optimal Network Analysis in Hierarchical Power Quad-Grids.
APCCAS
Jin-Tai Yan, Zhi-Wei Chen, Chia-Wei Wu, Ming-Yuen Wu
2006 C conf
Optimal shielding insertion for inductive noise avoidance.
ISCAS
Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen
2006 C conf
Timing-constrained yield-driven wire sizing for critical area minimization.
ISCAS
Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee
2006 — conf
Width and Timing-Constrained Wire Sizing for Critical Area Minimization.
APCCAS
Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang
2006 — conf
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis.
ICECS
Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen
2005 — conf
Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation.
ISCAS (3)
Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen
2005 — conf
Floorplan-aware Steiner tree reconstruction for optimal buffer insertion.
ICECS
Jin-Tai Yan, Chia-Fang Lee, Tzu-Ya Wang
2005 — conf
LB-packing-based floorplan design on DBL representation.
ICECS
Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo
2005 — conf
Probabilistic congestion prediction in hierarchical quad-grid model.
ISCAS (2)
Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu
2005 J jnl
Timing-Constrained Flexibility-Driven Routing Tree Construction.
IEICE Trans. Inf. Syst.
Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee
2005 — conf
Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points.
ISCAS (2)
Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee
2005 — conf
Wiring area optimization in floorplan-aware hierarchical power grids.
ISCAS (2)
Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen
2004 — conf
Timing-constrained congestion-driven global routing.
ASP-DAC
Jin-Tai Yan, Shun-Hua Lin
2002 — conf
Printed circuit board routing and package layout codesign.
APCCAS (1)
Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen
2000 J jnl
Three-layer bubble-sorting-based nonManhattan channel routing.
ACM Trans. Design Autom. Electr. Syst.
Jin-Tai Yan
1999 J jnl
An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement.
VLSI Design
Jin-Tai Yan
1999 J jnl
An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
1999 J jnl
An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan
1999 J jnl
Routability Crossing Distribution and Floating Pin Assignment for
VLSI Design
Jin-Tai Yan
1998 J jnl
Routing Space Estimation and Assignment for Macro-Cell Placement.
J. Circuits Syst. Comput.
Jin-Tai Yan
1996 Misc conf
A simple yet effective genetic approach for the orientation assignment on cell-based layout.
VLSI Design
Jin-Tai Yan
1996 J jnl
An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment.
VLSI Design
Jin-Tai Yan, Pei-Yung Hsiao
1996 — conf
An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement.
Great Lakes Symposium on VLSI
Jin-Tai Yan
1996 J jnl
Minimizing the number of switchboxes for region definition and ordering assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Tai Yan, Pei-Yung Hsiao
1995 Misc conf
A new fuzzy-clustering-based approach for two-way circuit partitioning.
VLSI Design
Jin-Tai Yan, Pei-Yung Hsiao
1995 — conf
An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement.
Great Lakes Symposium on VLSI
Jin-Tai Yan
1995 C conf
An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering.
ICCD
Jin-Tai Yan
1995 C conf
Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning.
ICCD
Jin-Tai Yan
1995 — conf
Region definition and ordering assignment with the minimization of the number of switchboxes.
ASP-DAC
Jin-Tai Yan
1994 J jnl
A Fuzzy Clustering Algorithm for Graph Bisection.
Inf. Process. Lett.
Jin-Tai Yan, Pei-Yung Hsiao
1994 C conf
Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing.
ISCAS
Paul-Waie Shew, Jin-Tai Yan, Pei-Yung Hsiao, Yong-Ching Lim
1994 C conf
Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment.
ISCAS
Jin-Tai Yan, Pei-Yung Hsiao
1994 — conf
Routability crossing distribution and floating terminal assignment of T-type junction region.
Great Lakes Symposium on VLSI
Jin-Tai Yan, Pei-Yung Hsiao
1993 J jnl
A robust over-the-cell channel router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lih-Der Chang, Pei-Yung Hsiao, Jin-Tai Yan, Paul-Waie Shew