Jin-Fu Lin

11 papers C 1Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2018 — conf
Cross-Domain Hallucination Network for Fine-Grained Object Recognition.
CVPR Workshops
Jin-Fu Lin, Yen-Liang Lin, Erh-Kan King, Hung-Ting Su, Winston H. Hsu
2015 J jnl
Topology algorithm based on link maintenance time for mobile ad hoc using directional antennas.
Int. J. Wirel. Mob. Comput.
Jin-Fu Lin, Peng Bai, Jian-Xun Wang, Ying Wang, Tao Wang
2012 — conf
A 1-V CDS bandgap reference without on-chip resistors.
APCCAS
Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, Jin-Fu Lin
2012 — conf
A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology.
APCCAS
Sheng-Hsiung Lin, Jin-Fu Lin, Guan-Ying Huang, Soon-Jyh Chang
2011 J jnl
A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages.
IEICE Trans. Electron.
Jin-Fu Lin, Soon-Jyh Chang
2011 J jnl
Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs.
J. Electron. Test.
Jin-Fu Lin, Hsin-Wen Ting
2011 J jnl
Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, Chih-Hao Huang
2010 J jnl
A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, Chih-Hao Huang
2009 — conf
Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique.
Asian Test Symposium
Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang
2008 — conf
A Reduced Code Linearity Test Method for Pipelined A/D Converters.
ATS
Jin-Fu Lin, Te-Chieh Kung, Soon-Jyh Chang
2006 C conf
A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique.
ISCAS
Jin-Fu Lin, Soon-Jyh Chang