Jin-Fu Li

135 papers A 14B 9C 1Misc 12Journal 41Unranked 58
YearRankTypeTitle / Venue / Authors
2025 — conf
Fault-Aware Repair Scheme for Inter-Die Interconnects of Chiplet-Based Chips.
ATS
Yi-Chun Huang, Jin-Fu Li, Hong-Siang Fu, Yung-Ping Lee
2025 J jnl
Hardware Trojan Design With Low Overhead and High Destructiveness for STT-MRAM-Based CIMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei-Che Cheng, Shih-Hsu Huang, Jin-Fu Li
2025 B conf
Local Trimming Method for Enhancing the Read Reliability of STT-MRAMs.
ETS
Pei-Yun Lin, Jin-Fu Li
2025 — conf
Special Session: Effective Design, Modeling and Testing Techniques for Digital Computing-in Memories with MAC Function.
DFT
Jin-Fu Li, Chun-Lung Hsu, Yu-Guang Chen, Ting-Yi Wu, Wei-Hung Lin, Shih-Hsu Huang, Yung-Chi Chia, Yu-Chieh Chen
2024 A conf
Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips.
ITC
Yi-Chun Huang, Pei-Yun Lin, Jin-Fu Li, Hong-Siang Fu, Yung-Ping Lee
2024 B conf
Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs.
ETS
Pei-Yun Lin, Jin-Fu Li
2024 — conf
Special Session: Testing of Digital Computing-In Memories with MAC Function.
DFT
Jin-Fu Li
2023 — conf
An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs.
ASP-DAC
Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li
2023 — conf
Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs.
ITC-Asia
Meng-Shan Wu, Yen-Lin Chua, Jin-Fu Li, Yun-Ting Chuan, Shih-Hsu Huang
2023 — conf
Hardware Trojans of Computing-In-Memories: Issues and Methods.
DFT
Shih-Hsu Huang, Wei-Che Cheng, Jin-Fu Li
2023 — conf
Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability.
DFT
Jin-Fu Li
2022 A conf
DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs.
ITC
Ze-Wei Pan, Jin-Fu Li
2022 — conf
Design and Dataflow for Multibit SRAM-Based MAC Operations.
ISOCC
Chuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li
2022 — conf
Design and Test of Computing-In Memories.
ISOCC
Jin-Fu Li
2022 — conf
Fault Modeling and Testing of RRAM-based Computing-In Memories.
ITC-Asia
Yu-cheng Yang, Jin-Fu Li
2022 — conf
Foreword: ATS 2022.
ATS
Jin-Fu Li, Jing-Jia Liou
2022 — conf
Testing and Reliability of Computing-In Memories: Solutions and Challenges.
ITC-Asia
Jin-Fu Li
2021 — conf
An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing.
DFT
Wei Chang, Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li
2021 — conf
Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults.
SoCC
Yung-Yu Tsai, Jin-Fu Li
2020 — conf
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method.
ITC-Asia
Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2020 — conf
Testing of Configurable 8T SRAMs for In-Memory Computing.
ATS
Jin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun
2019 — conf
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered.
3DIC
Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li
2019 — conf
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs.
3DIC
Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang
2019 — conf
Testing of In-Memory-Computing 8T SRAMs.
DFT
Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
2019 — conf
Testing stuck-open faults of priority address encoder in content addressable memories.
ASP-DAC
Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
2018 — conf
A channel-sharable built-in self-test scheme for multi-channel DRAMs.
ASP-DAC
Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou
2018 J jnl
Conference Reports: Report on 2017 IEEE Asian Test Symposium.
IEEE Des. Test
Jin-Fu Li, Jiun-Lang Huang
2018 — conf
Diagnosis of Resistive Nonvolatile-8T SRAMs.
ISOCC
Yu-Ting Li, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
2018 B conf
Modeling and testing comparison faults of memristive ternary content addressable memories.
ETS
Li-Wei Deng, Jin-Fu Li, Yong-Xiao Chen
2017 B conf
A built-in self-test scheme for classifying refresh periods of DRAMs.
ETS
Chia-Ming Chang, Yong-Xiao Chen, Jin-Fu Li
2017 — conf
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs.
ITC-Asia
Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2016 — conf
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories.
ATS
Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2016 B conf
A built-in method for measuring the delay of TSVs in 3D ICs.
ETS
Han-Yu Wu, Yong-Xiao Chen, Jin-Fu Li
2016 A conf
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.
ITC
Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2016 Misc conf
Fault modeling and testing of resistive nonvolatile-8T SRAMs.
VTS
Yu-Ting Li, Yong-Xiao Chen, Jin-Fu Li
2015 — conf
A hybrid built-in self-test scheme for DRAMs.
VLSI-DAT
Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou
2015 Misc conf
Fault modeling and testing of 1T1R memristor memories.
VTS
Yong-Xiao Chen, Jin-Fu Li
2015 J jnl
Hierarchical Test Integration Methodology for 3-D ICs.
IEEE Des. Test
Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2015 J jnl
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Chih-Sheng Hou, Jin-Fu Li
2015 — conf
Testing Inter-Word Coupling Faults of Wide I/O DRAMs.
ATS
Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li
2014 J jnl
A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Sheng Hou, Jin-Fu Li, Ting-Jun Fu
2014 — conf
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.
ATS
Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2014 — conf
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.
ATS
Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo
2014 J jnl
Testing Disturbance Faults in Various NAND Flash Memories.
J. Electron. Test.
Chih-Sheng Hou, Jin-Fu Li
2014 — conf
Testing of Non-volatile Logic-Based System Chips.
ATS
Yong-Xiao Chen, Jin-Fu Li
2014 A conf
The overview of 2014 CAD contest at ICCAD.
ICCAD
Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li
2014 J jnl
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs.
ACM Trans. Embed. Comput. Syst.
Yu-Jen Huang, Jin-Fu Li
2013 J jnl
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Che-Wei Chou, Yu-Jen Huang, Jin-Fu Li
2013 J jnl
A Self-Repair Technique for Content Addressable Memories with Address-Input-Free Writing Function.
J. Inf. Sci. Eng.
Chun-Kai Lai, Yu-Jen Huang, Jin-Fu Li
2013 — conf
A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs.
Asian Test Symposium
Chi-Chun Yang, Che-Wei Chou, Jin-Fu Li
2013 Misc conf
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.
VTS
Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013 Misc conf
Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs.
VTS
Chih-Sheng Hou, Jin-Fu Li
2013 — conf
An FPGA-based test platform for analyzing data retention time distribution of DRAMs.
VLSI-DAT
Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013 Misc conf
Special session 4C: Hot topic 3D-IC design and test.
VTS
Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai
2013 — conf
Testing Disturbance Faults in Various NAND Flash Memories.
Asian Test Symposium
Chih-Sheng Hou, Jin-Fu Li
2012 J jnl
A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines.
IEEE Trans. Very Large Scale Integr. Syst.
Shun-Hsun Yang, Yu-Jen Huang, Jin-Fu Li
2012 A conf
A built-in self-test scheme for 3D RAMs.
ITC
Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2012 — conf
Area and reliability efficient ECC scheme for 3D RAMs.
VLSI-DAT
Li-Jung Chang, Yu-Jen Huang, Jin-Fu Li
2012 J jnl
Built-In Self-Repair Scheme for the TSVs in 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Jen Huang, Jin-Fu Li
2012 J jnl
Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng
2012 B conf
Disturbance fault testing on various NAND flash memories.
ETS
Chih-Sheng Hou, Jin-Fu Li
2012 J jnl
Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers.
IEEE Trans. Very Large Scale Integr. Syst.
Yu-Jen Huang, Jin-Fu Li
2012 — conf
On test and repair of 3D random access memory.
ASP-DAC
Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li
2012 — conf
Post-bond test techniques for TSVs with crosstalk faults in 3D ICs.
VLSI-DAT
Yu-Jen Huang, Jin-Fu Li, Che-Wei Chou
2012 Misc conf
Test cost optimization technique for the pre-bond test of 3D ICs.
VTS
Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li
2012 J jnl
Testing and Diagnosing Comparison Faults of TCAMs with Asymmetric Cells.
IEEE Trans. Computers
Jin-Fu Li
2011 J jnl
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Tsu-Wei Tseng, Jin-Fu Li
2011 Misc conf
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.
VTS
Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2011 J jnl
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng
2011 J jnl
SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories.
J. Inf. Sci. Eng.
Tsu-Wei Tseng, Jin-Fu Li
2010 J jnl
A Built-in Method to Repair SoC RAMs in Parallel.
IEEE Des. Test Comput.
Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou
2010 — conf
A Test Integration Methodology for 3D Integrated Circuits.
Asian Test Symposium
Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2010 B conf
A low-cost and scalable test architecture for multi-core chips.
ETS
Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li
2010 B conf
A low-cost built-in self-test scheme for an array of memories.
ETS
Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li
2010 Misc conf
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.
VTS
Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li
2010 J jnl
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li
2010 — conf
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs.
SoCC
Yu-Jen Huang, Yun-Chao You, Jin-Fu Li
2010 — conf
Is 3D integration an opportunity or just a hype?
ASP-DAC
Jin-Fu Li, Cheng-Wen Wu
2010 J jnl
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs.
IEEE Trans. Very Large Scale Integr. Syst.
Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu
2010 J jnl
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou
2010 — conf
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs.
DELTA
Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou
2010 J jnl
Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fu Li
2010 J jnl
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Fu Li, Yu-Jen Huang, Yong-Jyun Hu
2009 C conf
A Programmable Online/Off-line Built-in Self-test Scheme for RAMs with ECC.
ISCAS
Hsing-Chen Lu, Jin-Fu Li
2009 — conf
Efficient diagnosis algorithms for drowsy SRAMs.
ISQED
Bing-Wei Huang, Jin-Fu Li
2009 J jnl
Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks.
IEEE Micro
Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li
2009 Misc conf
Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells.
VTS
Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li
2009 — conf
Testability Exploration of 3-D RAMs and CAMs.
Asian Test Symposium
Yu-Jen Huang, Jin-Fu Li
2008 J jnl
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy.
J. Electron. Test.
Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang
2008 — conf
A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips.
ATS
Yu-Jen Huang, Jin-Fu Li
2008 J jnl
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs.
IEICE Trans. Inf. Syst.
Hong-Ming Shieh, Jin-Fu Li
2008 A conf
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs.
ITC
Tsu-Wei Tseng, Jin-Fu Li
2007 Misc conf
A Built-In Self-Repair Scheme for Multiport RAMs.
VTS
Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen
2007 J jnl
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jin-Fu Li, Chao-Da Huang
2007 J jnl
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
CoRR
Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
2007 — conf
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs.
ATS
Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu
2007 — conf
Design of cost-efficient memory-based FFT processors using single-port memories.
SoCC
Yao-Xian Yang, Jin-Fu Li, Hsiang-Ning Liu, Chin-Long Wey
2007 — conf
Diagnosing scan chains using SAT-based diagnostic pattern generation.
SoCC
Jin-Fu Li, Feijun (Frank) Zheng, Kwang-Ting Cheng
2007 J jnl
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst.
Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng
2007 J jnl
Raisin: Redundancy Analysis Algorithm Simulation.
IEEE Des. Test Comput.
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2007 — conf
Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells.
ATS
Jin-Fu Li
2007 J jnl
Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Fu Li
2007 J jnl
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults.
IET Comput. Digit. Tech.
Yu-Jen Huang, Jin-Fu Li
2007 J jnl
Transparent-Test Methodologies for Random Access Memories Without/With ECC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin-Fu Li
2006 — conf
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy.
DFT
Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li
2006 A conf
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.
ITC
Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen
2006 A conf
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap.
DATE
Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang
2006 B conf
Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories.
ETS
Yu-Jen Huang, Jin-Fu Li
2006 — conf
Verification Methodology for Self-Repairable Memory Systems.
ATS
Jin-Fu Li, Chun-Hsien Wu
2005 J jnl
A built-in self-repair design for RAMs with 2-D redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
2005 — conf
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability.
ISCAS (1)
Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang
2005 A conf
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories.
DATE
Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
2005 — conf
An error detection and correction scheme for RAMs with partial-write function.
MTDT
Jin-Fu Li, Yu-Jane Huang
2005 Misc conf
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories.
VTS
Jin-Fu Li, Chou-Kun Lin
2005 — conf
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs.
ASP-DAC
Jin-Fu Li
2005 A conf
Testing priority address encoder faults of content addressable memories.
ITC
Jin-Fu Li
2004 — conf
An Efficient Diagnosis Scheme for Random Access Memories.
Asian Test Symposium
Jin-Fu Li, Chao-Da Huang
2004 J jnl
Diagnosing Binary Content Addressable Memories with Comparison and RAM Faults.
IEICE Trans. Inf. Syst.
Jin-Fu Li
2004 — conf
Efficient Test Methodologies for Conditional Sum Adders.
Asian Test Symposium
Jin-Fu Li, Chih-Chiang Hsu
2003 A conf
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.
ITC
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow
2003 — conf
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.
MTDT
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li
2003 J jnl
Built-in redundancy analysis for memory yield improvement.
IEEE Trans. Reliab.
Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
2003 J jnl
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories.
J. Electron. Test.
Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
2002 J jnl
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.
J. Electron. Test.
Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
2002 J jnl
A Hierarchical Test Methodology for Systems on Chip.
IEEE Micro
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
2002 A conf
A Hierarchical Test Scheme for System-On-Chip Designs.
DATE
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
2002 — conf
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
IOLTW
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2002 — conf
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
MTDT
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2002 J jnl
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.
J. Electron. Test.
Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
2002 J jnl
Efficient FFT network testing and diagnosis schemes.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fu Li, Cheng-Wen Wu
2002 Misc conf
Testing and Diagnosing Embedded Content Addressable Memories.
VTS
Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
2001 A conf
March-based RAM diagnosis algorithms for stuck-at and coupling faults.
ITC
Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2001 A conf
Memory fault diagnosis by syndrome compression.
DATE
Jin-Fu Li, Cheng-Wen Wu
2000 — conf
A built-in self-test and self-diagnosis scheme for embedded SRAM.
Asian Test Symposium
Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
1999 — conf
Testable and Fault Tolerant Design for FFT Networks.
DFT
Jin-Fu Li, Cheng-Wen Wu