Jin-Fa Lin

24 papers C 3Journal 15Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
A low power sense-amplifier-based flip-flop with conditional transition detection scheme for low voltage applications.
Integr.
Yao-Hsuan Ku, Cheng-Hsueh Yang, Jin-Fa Lin
2025 J jnl
Safety Monitoring System of Stamping Presses Based on YOLOv8n Model.
IEEE Access
Tsoi-Na Fung, Yao-Hsuan Ku, Yu-Wei Chou, He-Shiang Yu, Jin-Fa Lin
2022 J jnl
Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design.
Sensors
Jin-Fa Lin, Zheng-Jie Hong, Jun-Ting Wu, Xin-You Tung, Cheng-Hsueh Yang, Yu-Cheng Yen
2021 J jnl
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.
Sensors
Ming-Hwa Sheu, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin, Jin-Fa Lin
2021 — conf
A 0.5V True-Single-Phase 16T Flip-Flop in 180-nm CMOS for IoT Applications.
ICCE-TW
Zhi-Zhong Wang, Yi-Hsuan Hung, Jun-Ting Wu, Zheng-Jie Hong, Jin-Fa Lin
2020 — conf
Semantic Lung Segmentation Using Convolutional Neural Networks.
Bildverarbeitung für die Medizin
Ching-Sheng Chang, Jin-Fa Lin, Ming-Ching Lee, Christoph Palm
2019 J jnl
Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design.
IEICE Trans. Electron.
Po-Yu Kuo, Chia-Hsin Hsieh, Jin-Fa Lin, Ming-Hwa Sheu, Yi-Ting Hung
2019 — conf
Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation.
ISOCC
Wei-Hsuan Ma, Kuan-Ying Chang, Kuan-Ting Chen, Yin-Tsung Hwang, Jin-Fa Lin
2018 C conf
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.
ISCAS
Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu
2017 J jnl
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai
2016 J jnl
Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors.
J. Low Power Electron.
Jin-Fa Lin, Ming-Yan Tsai, Kun-Sheng Li, Yun-Rong Jiang, Yu-Shiang Cheng
2016 — conf
MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging.
APCCAS
Shin-Shiang Wang, Yi-Chi Tien, Yin-Tsung Hwang, Jin-Fa Lin, Guo-Zua Wu
2014 J jnl
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through.
IEEE Trans. Very Large Scale Integr. Syst.
Jin-Fa Lin
2012 J jnl
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique.
IEEE Trans. Very Large Scale Integr. Syst.
Yin-Tsung Hwang, Jin-Fa Lin
2012 C conf
Low power 10-transistor full adder design based on degenerate pass transistor logic.
ISCAS
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
2012 J jnl
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu
2010 J jnl
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
2010 J jnl
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
2010 J jnl
Low Power Pulse Generator Design Using Hybrid Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
2008 J jnl
Low Complexity Dual-Mode Pulse Generator Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
2007 J jnl
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho
2007 — conf
Low Power Multipliers Using Enhenced Row Bypassing Schemes.
SiPS
Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu
2006 C conf
A high speed and energy efficient full adder design using complementary & level restoring carry logic.
ISCAS
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho
2006 — conf
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.
APCCAS
Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu