Jim Tschanz - RankMe

11 papers A 1Journal 2Unranked 8

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	A 5.4V-Vin, 9.3A/mm VLSI Technology and Circuits Sally Amin, Harish Krishnamurthy, Huong T. Do, Claudio Alvarez, Mike Hill, Kaladhar Radhakrishnan, Vivek De, Sheldon Weng, Krishnan Ravichandran, Jim Tschanz, Wilfred Gomes, Jonathan Douglas
2023	—	`conf`	A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De
2022	—	`conf`	Innovations for Intelligent Edge. ESSCIRC Vida Ilderem, Stefano Pellerano, Jim Tschanz, Tanay Karnik, Vivek De
2020	—	`conf`	A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De
2020	—	`conf`	Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De
2017	—	`conf`	20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. ISSCC Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De
2015	—	`conf`	A fully integrated charge sharing active decap scheme for power supply noise suppression. SoCC Ahmed M. Ammar, Rafik Guindi, Ethan Shih, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah
2013	A	`conf`	Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz
2012	—	`conf`	A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz
2011	J	`jnl`	Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2009	J	`jnl`	Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design. IEEE Des. Test Comput. Yu Cao, Jim Tschanz, Pradip Bose