Jim D. Garside

81 papers A* 1A 3B 2C 14Misc 3Journal 24Unranked 34

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. CoRR Sebastian Höppner, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Marco Stolba, Florian Kelber, Bernhard Vogginger, Felix Neumärker, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Thomas Hocker, Dennis Walter, Gengting Liu, Jim D. Garside, Steve B. Furber, Christian Mayr
2020	J	`jnl`	Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks. Simul. Model. Pract. Theory Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
2020	J	`jnl`	spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System. IEEE Access Luis A. Plana, Jim D. Garside, Jonathan Heathcote, Jeffrey Pepper, Steve Temple, Simon Davidson, Mikel Luján, Steve B. Furber
2019	J	`jnl`	Dynamic Power Management for Neuromorphic Many-Core Systems. CoRR Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumaerker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr
2019	J	`jnl`	Dynamic Power Management for Neuromorphic Many-Core Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr
2018	C	`conf`	Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip. ARITH Mantas Mikaitis, David R. Lester, Delong Shang, Steve B. Furber, Gengting Liu, Jim D. Garside, Stefan Scholze, Sebastian Höppner, Andreas Dixius
2018	J	`jnl`	Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application. IEEE Trans. Biomed. Circuits Syst. Robert James, Jim D. Garside, Luis A. Plana, Andrew Rowley, Steve B. Furber
2017	B	`conf`	Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. FPL Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch
2017	C	`conf`	Dynamic voltage and frequency scaling for neuromorphic many-core systems. ISCAS Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber
2017	J	`jnl`	Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
2017	B	`conf`	HyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation. VEE Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, John Goodacre, Mikel Luján
2017	C	`conf`	Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. ISCAS Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Prateek Joshi, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber
2017	A*	`conf`	Low overhead dynamic binary translation on ARM. PLDI Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, Mikel Luján
2017	—	`conf`	Parallel distribution of an inner hair cell and auditory nerve model for real-time application. BioCAS Robert James, Jim D. Garside, Michael Hopkins, Luis A. Plana, Steve Temple, Simon Davidson, Steve B. Furber
2016	—	`conf`	Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis. ACSD Mahdi Jelodari Mamaghani, Danil Sokolov, Jim D. Garside
2016	—	`conf`	Automatic Clock: A Promising Approach toward GALSification. ASYNC Mahdi Jelodari Mamaghani, Milos Krstic, Jim D. Garside
2016	—	`conf`	DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. MEMSYS Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
2016	—	`conf`	HAPPY: Hybrid Address-based Page Policy in DRAMs. MEMSYS Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
2016	C	`conf`	On-chip order-exploiting routing table minimization for a multicast supercomputer network. HPSR Andrew Mundy, Jonathan Heathcote, Jim D. Garside
2016	J	`jnl`	Optimizing Indirect Branches in Dynamic Binary Translators. ACM Trans. Archit. Code Optim. Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, Mikel Luján
2016	Misc	`conf`	Parallel Hardware Merge Sorter. FCCM Wei Song, Dirk Koch, Mikel Luján, Jim D. Garside
2015	Misc	`conf`	Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. FCCM Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
2015	—	`conf`	Analysis of FPGA and software approaches to simulate unconventional computer architectures. ReConFig Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
2015	J	`jnl`	DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. CoRR Mohsen Ghasempour, Jim D. Garside, Aamer Jaleel, Mikel Luján
2015	A	`conf`	De-elastisation: from asynchronous dataflows to synchronous circuits. DATE Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards
2015	—	`conf`	Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults. ASYNC Guangda Zhang, Jim D. Garside, Wei Song, Javier Navaridas, Zhiying Wang
2015	J	`jnl`	HAPPY: Hybrid Address-based Page Policy in DRAMs. CoRR Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
2015	J	`jnl`	SpiNNaker - Programming Model. IEEE Trans. Computers Andrew D. Brown, Stephen B. Furber, Jeffrey S. Reeve, Jim D. Garside, Kier J. Dugan, Luis A. Plana, Steve Temple
2014	—	`conf`	An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults. ASYNC Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
2014	C	`conf`	Automatic data path extraction in large-scale register-transfer level designs. ISCAS Wei Song, Jim D. Garside, Doug A. Edwards
2014	—	`conf`	On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip. ACM Great Lakes Symposium on VLSI Wei Song, Guangda Zhang, Jim D. Garside
2014	C	`conf`	Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. DSD Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards
2014	J	`jnl`	Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. Microprocess. Microsystems Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
2013	C	`conf`	Automatic Controller Detection for Large Scale RTL Designs. DSD Wei Song, Jim D. Garside
2013	J	`jnl`	Overview of the SpiNNaker System Architecture. IEEE Trans. Computers Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown
2013	J	`jnl`	SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. IEEE J. Solid State Circuits Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R. Lester, Andrew D. Brown, Steve B. Furber
2013	J	`jnl`	SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. Parallel Comput. Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang
2013	C	`conf`	Transient Fault Tolerant QDI Interconnects Using Redundant Check Code. DSD Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
2012	—	`conf`	An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. ASYNC Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana
2012	A	`conf`	Area efficient asynchronous SDM routers using 2-stage Clos switches. DATE Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge
2012	—	`conf`	Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration. ARC Geoffrey Ndu, Jim D. Garside
2012	J	`jnl`	Scalable communications for a million-core neural processing architecture. J. Parallel Distributed Comput. Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve B. Furber
2012	—	`conf`	SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. CICC Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve B. Furber
2011	J	`jnl`	SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge
2009	—	`conf`	A Programmable Adaptive Router for a GALS Parallel System. ASYNC Jian Wu, Steve B. Furber, Jim D. Garside
2009	—	`conf`	Fault Tolerant Delay Insensitive Inter-chip Communication. ASYNC Yebin Shi, Steve B. Furber, Jim D. Garside, Luis A. Plana
2009	—	`conf`	The Amulet chips: Architectural development for asynchronous microprocessors. ICECS Jim D. Garside, Stephen B. Furber, Steve Temple, Viv Woods
2008	—	`conf`	An adaptive bloom filter cache partitioning scheme for multicore architectures. ICSAMOS Konstantinos Nikas, Matthew Horsnell, Jim D. Garside
2007	—	`conf`	Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. ACM Great Lakes Symposium on VLSI Andrew Robinson, Jim D. Garside
2006	J	`jnl`	Modernization of teaching in embedded systems design - an international collaborative project. IEEE Trans. Educ. Saeid Nooshabadi, Jim D. Garside
2005	—	`conf`	A Low-Power Processor Architecture Optimized forWireless Devices. ASAP Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou
2005	Misc	`conf`	A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. VLSI Design Charlie Brej, Jim D. Garside
2004	J	`jnl`	A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. Very Large Scale Integr. Syst. Aristides Efthymiou, Jim D. Garside
2004	—	`conf`	An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury
2003	—	`conf`	Adaptive Pipeline Structures fo Speculation Control. ASYNC Aristides Efthymiou, Jim D. Garside
2003	J	`jnl`	An asynchronous copy-back cache architecture. Microprocess. Microsystems Daranee Hormdee, Jim D. Garside, Stephen B. Furber
2003	J	`jnl`	SPA - a secure Amulet core for smartcard applications. Microprocess. Microsystems Luis A. Plana, Peter A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu
2002	C	`conf`	Adaptive Pipeline Depth Control for Processor Power-Management. ICCD Aristides Efthymiou, Jim D. Garside
2002	C	`conf`	An Asynchronous Victim Cache. DSD Daranee Hormdee, Jim D. Garside, Stephen B. Furber
2002	A	`conf`	An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED Aristides Efthymiou, Jim D. Garside
2002	—	`conf`	Logic Design of Asynchronous Circuits (Tutorial Abstract). ASP-DAC/VLSI Design Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
2002	—	`conf`	SPA - A Synthesisable Amulet Core for Smartcard pplications. ASYNC W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Peter A. Riocreux, Luis A. Plana
2001	—	`conf`	A Practical Comparison of Asynchronous Design Styles. ASYNC David W. Lloyd, Jim D. Garside
2001	—	`conf`	AMULET3i Cache Architecture. ASYNC Daranee Hormdee, Jim D. Garside
2001	J	`jnl`	Power Management in the Amulet Microprocessors. IEEE Des. Test Comput. Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple
2000	C	`conf`	AMULET3: A 100 MIPS Asynchronous Embedded Processor. ICCD Stephen B. Furber, David A. Edwards, Jim D. Garside
2000	—	`conf`	AMULET3i - An Asynchronous System-on-Chip. ASYNC Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, Siamak Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli
1999	—	`conf`	AMULET3 Revealed. ASYNC Jim D. Garside, Stephen B. Furber, S.-H. Chung
1999	—	`conf`	Memory Faults in Asynchronous Microprocessors. ASYNC David W. Lloyd, Jim D. Garside, D. A. Gilbert
1999	—	`conf`	Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ASYNC Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury
1998	C	`conf`	AMULET3: a high-performance self-timed ARM microprocessor. ICCD Stephen B. Furber, Jim D. Garside, D. A. Gilbert
1998	J	`jnl`	Asynchronous Embedded Control. Integr. Comput. Aided Eng. Stephen B. Furber, Jim D. Garside, Steve Temple, Paul Day, Nigel C. Paver
1997	—	`conf`	A Result Forwarding Mechanism for Asynchronous Pipelined Systems. ASYNC D. A. Gilbert, Jim D. Garside
1997	J	`jnl`	AMULET1: A Asynchronous ARM Microprocessor. IEEE Trans. Computers John V. Woods, Paul Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple
1997	—	`conf`	AMULET2e: An Asynchronous Embedded Controller. ASYNC Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver
1996	—	`conf`	The AMULET2e cache system. ASYNC Jim D. Garside, Steve Temple, Rahul Mehra
1994	—	`conf`	AMULET1: A Micropipelined ARM. COMPCON Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods
1994	C	`conf`	The Design and Evaluation of an Asynchronous Microprocessor. ICCD Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods
1993	—	`conf`	A CMOS VLSI Implementation of an Asynchronous ALU. Asynchronous Design Methodologies Jim D. Garside
1993	—	`conf`	A micropipelined ARM. VLSI Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods
1992	C	`conf`	Register Locking in an Asynchronous Microprocessor. ICCD N. C. Paver, Paul Day, Stephen B. Furber, Jim D. Garside, John V. Woods