Jihyun Cho

15 papers C 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2018 J jnl
Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals.
IEEE J. Solid State Circuits
Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon
2018 J jnl
Modular 128-Channel Δ-ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems.
IEEE J. Solid State Circuits
Sung-Yun Park, Jihyun Cho, Kyounghwan Na, Euisik Yoon
2016 J jnl
A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression.
IEEE J. Solid State Circuits
Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Vivek Nagaraj, Theoden I. Netoff, Michael P. Flynn, Euisik Yoon
2015 — conf
12.3 PWM buck converter with >80% PCE in 45μA-to-4mA loads using analog-digital hybrid control for impiantale biomedical systems.
ISSCC
Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon
2015 J jnl
A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems.
IEEE Trans. Biomed. Circuits Syst.
Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon
2015 J jnl
An Energy/Illumination-Adaptive CMOS Image Sensor With Reconfigurable Modes of Operations.
IEEE J. Solid State Circuits
Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon
2015 — conf
Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression.
VLSIC
Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Cynthia A. Chestek, Michael P. Flynn, Euisik Yoon
2015 — conf
Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ analog front-end architecture with 4.84fJ/C-s·mm
VLSIC
Sung-Yun Park, Jihyun Cho, Kyounghwan Na, Euisik Yoon
2014 — conf
7.2 243.3pJ/pixel bio-inspired time-stamp-based 2D optic flow sensor for artificial compound eyes.
ISSCC
Seokjun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon
2014 J jnl
A 3-D Camera With Adaptable Background Light Suppression Using Pixel-Binning and Super-Resolution.
IEEE J. Solid State Circuits
Jihyun Cho, Jaehyuk Choi, Seong-Jin Kim, Seokjun Park, Jungsoon Shin, James D. K. Kim, Euisik Yoon
2014 J jnl
A 3.4-µW Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging.
IEEE J. Solid State Circuits
Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon
2013 — conf
A 3.4µW CMOS image sensor with embedded feature-extraction algorithm for motion-triggered object-of-interest imaging.
ISSCC
Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon
2012 — conf
A 1.36μW adaptive CMOS image sensor with reconfigurable modes of operation from available energy/illumination for distributed wireless sensor network.
ISSCC
Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon
2008 — conf
A 5000S/s Single-Chip Smart Eye-Tracking Sensor.
ISSCC
Dongsoo Kim, Jihyun Cho, Seunghyun Lim, Dongmyung Lee, Gunhee Han
2006 C conf
CMOS image sensor with analog gamma correction using nonlinear single-slope ADC.
ISCAS
Seogheon Ham, Yonghee Lee, Wunki Jung, Seunghyun Lim, Kwisung Yoo, Youngcheol Chae, Jihyun Cho, Dongmyung Lee, Gunhee Han