Jihang Gao

20 papers C 1Journal 7Unranked 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Highly Power-Efficient Input-Boosted First Stage for Capacitively Coupled Chopper Instrumentation Amplifiers.
IEEE J. Solid State Circuits
Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Linxiao Shen
2026 J jnl
An 8b 1-GS/s SAR ADC With Comparison Time Quantizer, Metastability Reduction, and On-Chip Self-Tuning Delay Achieving 47.2-dB SNDR at Nyquist Input.
IEEE J. Solid State Circuits
Jie Li, Siyuan Ye, Zhuoyi Chen, Jihang Gao, Xinhang Xu, Linxiao Shen
2026 J jnl
An Area-Efficient Noise-Shaping SAR ADC Utilizing Dynamic Common-Gate Amplifier With Charge-Boosted Amplification and Dynamic-Bulk-Switching.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiajia Cui, Jihang Gao, Xinhang Xu, Yandong He, Linxiao Shen
2025 — conf
18.2 A 12.2μW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD ΔΣM with Gain-Embedded Bootstrapped Sampler.
ISSCC
Yaohui Luan, Xinhang Xu, Jihang Gao, Jiajia Cui, Zhuoyi Chen, Siyuan Ye, Ru Huang, Linxiao Shen
2025 — conf
18.3: A 93.3dB SNDR, 180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch-Error-Shaping Technique and Negative-R-Assisted Residue Integrator.
ISSCC
Jihang Gao, Yaohui Luan, Siyuan Ye, Xinhang Xu, Zhuoyi Chen, Jiajia Cui, Ru Huang, Linxiao Shen
2025 — conf
18.5 A Rail-to-Rail 3
ISSCC
Siyuan Ye, Jiajia Cui, Jihang Gao, Jie Li, Xing Zhang, Ru Huang, Linxiao Shen
2025 — conf
A 110µW 99.5dB-SNDR 20kHz-BW Intrinsically Linear CTDSM with Hybrid Gm-Boosting OTA and Tri-Level FIR DACs.
CICC
Xinhang Xu, Yaohui Luan, Jie Li, Jihang Gao, Kwok Cheong Li, Jiajia Cui, Ru Huang, Linxiao Shen
2025 J jnl
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting.
IEEE J. Solid State Circuits
Siyuan Ye, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Yaohui Luan, Le Ye, Xing Zhang, Ru Huang, Linxiao Shen
2025 J jnl
A Calibration-Free Pipelined-SAR ADC With Cross-Stage Gain-Mismatch Error Shaping and Inherent Noise Shaping.
IEEE J. Solid State Circuits
Jihang Gao, Yaohui Luan, Siyuan Ye, Jiajia Cui, Xinhang Xu, Linxiao Shen
2025 J jnl
A Flying-Capacitor-Based Reset Scheme for Low Power Dynamic Comparator.
IEEE Trans. Circuits Syst. II Express Briefs
Kwok Cheong Li, Xinhang Xu, Jihang Gao, Siyuan Ye, Jiajia Cui, Yacong Zhang, Ru Huang, Linxiao Shen
2025 — conf
An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration.
ISSCC
Zhuoyi Chen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan, Ru Huang, Linxiao Shen
2025 J jnl
An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS.
IEEE J. Solid State Circuits
Jihang Gao, Siyuan Ye, Jie Li, Xinhang Xu, Zhuoyi Chen, Jiajia Cui, Yaohui Luan, Ru Huang, Le Ye, Linxiao Shen
2024 — conf
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.
ISSCC
Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Hao Zhang, Ru Huang, Linxiao Shen, Le Ye
2024 — conf
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.
ISSCC
Siyuan Ye, Linxiao Shen, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Hao Zhang, Xing Zhang, Le Ye, Ru Huang
2024 — conf
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.
ISSCC
Zhuoyi Chen, Linxiao Shen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan, Hao Zhang, Le Ye, Ru Huang
2024 — conf
An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input.
CICC
Jie Li, Linxiao Shen, Siyuan Ye, Jihang Gao, Jiajia Cui, Xinhang Xu, Zhuoyi Chen, Yaohui Luan, Yuanxin Bao, Ru Huang, Le Ye
2023 — conf
A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.
ESSCIRC
Xinhang Xu, Linxiao Shen, Siyuan Ye, Jiayi Wu, Zhuoyi Chen, Jihang Gao, Jiajia Cui, Yihan Zhang, Ru Huang, Le Ye
2023 — conf
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.
ISSCC
Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye
2022 C conf
A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique.
ISCAS
Xinhang Xu, Siyuan Ye, Jihang Gao, Yihan Zhang, Linxiao Shen, Le Ye
2022 — conf
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.
ISSCC
Yihan Zhang, Chang Xue, Xiao Wang, Tianyi Liu, Jihang Gao, Peiyu Chen, Jinguang Liu, Linan Sun, Linxiao Shen, Jiayoon Ru, Le Ye, Ru Huang