Jih-Sheng Shen

19 papers A* 1A 5C 2Journal 7Unranked 3

Year	Rank	Type	Title / Venue / Authors
2014	J	`jnl`	Dynamic partially reconfigurable architecture for fast Fourier transform computation. Int. J. Embed. Syst. Hung-Lin Chao, Cheng-Chien Wu, Chun-Yang Peng, Chun-Hsien Lu, Jih-Sheng Shen, Pao-Ann Hsiung
2014	J	`jnl`	Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. Jih-Sheng Shen, Pao-Ann Hsiung
2014	—	`conf`	Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture. HPCS Jih-Sheng Shen, Pao-Ann Hsiung, Juin-Ming Lu
2013	J	`jnl`	Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption. Comput. Electr. Eng. Jih-Sheng Shen, Pao-Ann Hsiung, Chun-Hsian Huang
2013	—	`conf`	Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design. FPT Hung-Lin Chao, Chun-Yang Peng, Cheng-Chien Wu, Ken-Shin Huang, Chun-Hsien Lu, Jih-Sheng Shen, Pao-Ann Hsiung
2011	—	`conf`	Network-on-Chip router design with Buffer-Stealing. ASP-DAC Wan-Ting Su, Jih-Sheng Shen, Pao-Ann Hsiung
2010	C	`conf`	A Self-Adaptive Hardware/Software System Architecture for Ubiquitous Computing Applications. UIC Chun-Hsian Huang, Jih-Sheng Shen, Pao-Ann Hsiung
2010	—	`book`	Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication. Jih-Sheng Shen, Pao-Ann Hsiung
2010	A	`conf`	Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip. DATE Jih-Sheng Shen, Chun-Hsian Huang, Pao-Ann Hsiung
2010	J	`jnl`	Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption. J. Syst. Archit. Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen
2010	J	`jnl`	Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. Pao-Ann Hsiung, Chun-Hsian Huang, Jih-Sheng Shen, Cheng-Chi Chiang
2010	J	`jnl`	UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems. J. Syst. Archit. Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen
2008	A	`conf`	A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability. ACSAC Jih-Sheng Shen, Pao-Ann Hsiung, Kuei-Chung Chang
2008	J	`jnl`	Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes. ACM Trans. Design Autom. Electr. Syst. Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
2006	A*	`conf`	Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. DAC Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
2006	A	`conf`	Fast Run-Time Power Monitoring Methodology for Embedded Systems. ESA Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
2006	C	`conf`	On a design of crossroad switches for low-power on-chip communication architectures. ISCAS Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen
2005	A	`conf`	A low-power crossroad switch architecture and its core placement for network-on-chip. ISLPED Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
2005	A	`conf`	Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems. ESA Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen