Jih-Nung Lee - RankMe

16 papers A 4Misc 5Journal 4Unranked 3

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
2022	J	`jnl`	Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
2021	Misc	`conf`	Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
2020	Misc	`conf`	CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
2019	Misc	`conf`	Layout-Based Dual-Cell-Aware Tests. VTS Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee
2019	A	`conf`	Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
2018	J	`jnl`	A Model-Based-Random-Forest Framework for Predicting V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chien-Hsueh Lin, Chih-Ying Tsai, Kao-Chi Lee, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao
2017	Misc	`conf`	Methodology of generating dual-cell-aware tests. VTS Yu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien, Ying-Yen Chen, Max Wu, Jih-Nung Lee, Mango C.-T. Chao
2017	—	`conf`	Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques. ASP-DAC Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao
2016	Misc	`conf`	Predicting Vt mean and variance from parallel Id measurement with model-fitting technique. VTS Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao
2015	—	`conf`	Case study of process and design performance debugging with Digital Speed Sensor. VLSI-DAT Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao
2014	J	`jnl`	Physical-aware systematic multiple defect diagnosis. IET Comput. Digit. Tech. Po-Juei Chen, Chieh-Chih Che, J. C.-M. Li, Shuo-Fen Kuo, Pei-Ying Hsueh, Chun-Yi Kuo, Jih-Nung Lee
2013	—	`conf`	Case study of yield learning through in-house flow of volume diagnosis. VLSI-DAT Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu
2009	A	`conf`	A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. ITC Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu
2003	A	`conf`	FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2003	A	`conf`	Fault Pattern Oriented Defect Diagnosis for Memories. ITC Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang