Jih-Ching Chiu

35 papers A 13B 2C 1Misc 1Journal 12Unranked 6

Year	Rank	Type	Title / Venue / Authors
2022	A	`conf`	Design and Implementation of the CNN Accelator Based on Multi-streaming SIMD Mechanisms. ICS Jih-Ching Chiu, Zhe-You Yan, Yung-Chi Liu
2022	A	`conf`	Design and Implementation of the Link-List DMA Controller for High Bandwidth Data Streaming. ICS Jih-Ching Chiu, Yan-Ting Wu, Yung-Chi Liu, Chi-Yang Hsieh
2022	A	`conf`	Design and Implementation of the Optimized Computing Architecture for Matrix Decomposition Algorithms. ICS Jih-Ching Chiu, Yu-Quen Chen, Yi-Xiang Wang, Yung-Chi Liu
2020	A	`conf`	Design and Implement Adaptive Tree Topology Mechanism For Wi-Fi Wireless Network. ICS Jih-Ching Chiu, Cheng-Lin Tsai, Zhi-Yu Lee
2020	A	`conf`	Design and Implement Robust Wireless Network Based on TCP Protocol. ICS Jih-Ching Chiu, Jun-Jiang Chen, Kuan-Lun Su
2020	A	`conf`	Design of Multidimension-media Streaming Protocol Based on RTSP. ICS Jih-Ching Chiu, Hao-Yu Tseng, Zhi-Yu Lee
2020	A	`conf`	The Brain Memory Architecture HW/SW Co-Design Platform with Adaptive CNN Algorithm. ICS Jih-Ching Chiu, Yu-Yi Wang, Wei-Yi Lin
2018	A	`conf`	Adaptive Linked-List Mechanism for Wi-Fi Wireless Network. ICS Tsung-Lin Lee, Jih-Ching Chiu, Yueh-Lin Li
2018	A	`conf`	Design and Implementation of Tree Topology Algorithm for Power Line Communication Network. ICS Guan-Jen Huang, Jih-Ching Chiu, Yueh-Lin Li
2018	A	`conf`	Design of Instruction Analyzer with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. ICS Yi-Xuan Lu, Jih-Ching Chiu, Shu-Jung Chao, Yong-Bin Ye
2014	Misc	`conf`	Design and implementation of sequential repair and backup routing protocol for wireless mesh network. ICNC Jih-Ching Chiu, Chun-Yao Zheng, Yao-Chin Huang, Kai-Ming Yang
2014	A	`conf`	Linked List Routing Algorithm with Wormhole Mechanism for Data Collecting Wireless Network. ICS Jih-Ching Chiu, Wen-Shin Wang, Chien-Lung Chen
2013	J	`jnl`	A hyperscalar dual-core architecture for embedded systems. Microprocess. Microsystems Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou
2013	J	`jnl`	A relation-exchanging buffering mechanism for instruction and data streaming. Comput. Electr. Eng. Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou, Chih-Kang Wu
2013	J	`jnl`	High-speed low-power multiplexer-based selector for priority policy. Comput. Electr. Eng. Jih-Ching Chiu, Kai-Ming Yang
2013	J	`jnl`	Two-Dimensional Interpolation-Assisted Channel Prediction for OFDM Systems. IEEE Trans. Broadcast. Hsuan-Chang Lee, Jih-Ching Chiu, Ken-Huang Lin
2012	—	`conf`	Analytical Modeling for Multi-transaction Bus on Distributed Systems. ICA3PP (2) Jih-Ching Chiu, Kai-Ming Yang, Chen-Ang Wong
2011	J	`jnl`	A Unitable Computing Architecture for Chip Multiprocessors. Comput. J. Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen, Ding-Siang Su
2010	J	`jnl`	A Novel instruction stream buffer for VLIW architectures. Comput. Electr. Eng. Jih-Ching Chiu, Kai-Ming Yang
2010	—	`conf`	A hyperscalar multi-core architecture. Conf. Computing Frontiers Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su
2010	J	`jnl`	A multi-streaming SIMD multimedia computing engine. Microprocess. Microsystems Jih-Ching Chiu, Yu-Liang Chou
2010	B	`conf`	Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture. ICPP Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen
2010	J	`jnl`	IRES: An integrated software and hardware interface framework for reconfigurable embedded system. IET Comput. Digit. Tech. Jih-Ching Chiu, Ta-Li Yeh
2010	J	`jnl`	The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. J. Inf. Sci. Eng. Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin
2009	—	`conf`	A multi-streaming SIMD architecture for multimedia applications. Conf. Computing Frontiers Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng
2009	A	`conf`	Design of a novel SIMD architecture by fusing operations and registers. ICS Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou
2009	—	`conf`	The Rendezvous Mechanism for the Multi-core AMBA System. ICPP Workshops Jih-Ching Chiu, Kai-Ming Yang, Mu-Chi Chang
2009	—	`conf`	The Software and Hardware Integration Linker for Reconfigurable Embedded System. CSE (2) Jih-Ching Chiu, Ta-Li Yeh, Mun-Kit Leong
2008	A	`conf`	Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA. ACSAC Jih-Ching Chiu, Yu-Liang Chou, Ta-Li Yeh, Tseng-Kuei Lin
2008	J	`jnl`	The Multi-context Reconfigurable Processing Unit for Fine-grain Computing. J. Inf. Sci. Eng. Jih-Ching Chiu, Yu-Liang Chou, Ren-Bang Lin
2005	—	`conf`	FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit. Asia-Pacific Computer Systems Architecture Conference Jih-Ching Chiu, Ren-Bang Lin
2003	J	`jnl`	Variable-size data item placement for load and storage balancing. J. Syst. Softw. Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung
2002	J	`jnl`	Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. J. Inf. Sci. Eng. Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung
2000	C	`conf`	Design of Instruction Stream Buffer with Trace Support for X86 Processors. ICCD Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung
1997	B	`conf`	Instruction Cache Prefetching with Extended BTB. ICPADS Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung