Jieh-Tsorng Wu

46 papers C 4Journal 27Unranked 15

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	A Digital Jitter Compensation Technique for Analog-to-Digital Converters. ISCAS Ding-Hao Wang, Jieh-Tsorng Wu
2023	—	`conf`	On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen
2021	J	`jnl`	An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. IEEE J. Solid State Circuits Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Yong Qu, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang
2019	J	`jnl`	A 1-V 175- $\mu$ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques. IEEE J. Solid State Circuits Sheng-Hui Liao, Jieh-Tsorng Wu
2019	—	`conf`	An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. ESSCIRC Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang
2018	—	`conf`	A 1 V 175 μW 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques. CICC Sheng-Hui Liao, Jieh-Tsorng Wu
2017	J	`jnl`	A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Chih-Min Chang, Jieh-Tsorng Wu
2016	C	`conf`	A computationally-efficient PWM technique for digital class-D amplifiers. ISCAS Chih-Min Chang, Jieh-Tsorng Wu
2015	J	`jnl`	A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Yung-Hui Chung, Jieh-Tsorng Wu
2015	J	`jnl`	Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Makoto Takamiya, Jieh-Tsorng Wu, Jussi Ryynänen, Kenichi Okada, Jaeha Kim
2013	C	`conf`	A 1-V 100-dB dynamic range 24.4-kHz bandwidth delta-sigma modulator. ISCAS Chia-Ling Chang, Jieh-Tsorng Wu
2013	J	`jnl`	A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation. IEEE J. Solid State Circuits Bing-Nan Fang, Jieh-Tsorng Wu
2013	J	`jnl`	A 81-dB Dynamic Range 16-MHz Bandwidth ΔΣ Modulator Using Background Calibration. IEEE J. Solid State Circuits Su-Hao Wu, Jieh-Tsorng Wu
2013	—	`conf`	Background calibration of integrator leakage in discrete-time delta-sigma modulators. NEWCAS Su-Hao Wu, Jieh-Tsorng Wu
2013	—	`conf`	F6: Mixed-signal/RF design and modeling in next-generation CMOS. ISSCC Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu
2012	C	`conf`	A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps. ISCAS Bing-Nan Fang, Jieh-Tsorng Wu
2012	—	`conf`	A 5.37mW 10b 200MS/s dual-path pipelined ADC. ISSCC Yun Chai, Jieh-Tsorng Wu
2012	J	`jnl`	A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC. IEEE J. Solid State Circuits Yun Chai, Jieh-Tsorng Wu
2011	J	`jnl`	A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz. IEEE J. Solid State Circuits Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu
2011	—	`conf`	A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz. ISSCC Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu
2011	J	`jnl`	A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques. IEEE J. Solid State Circuits Chun-Cheng Huang, Chung-Yi Wang, Jieh-Tsorng Wu
2011	J	`jnl`	A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero. IEEE Trans. Circuits Syst. II Express Briefs Wei-Hsin Tseng, Jieh-Tsorng Wu, Yung-Cheng Chu
2010	J	`jnl`	A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC. IEEE J. Solid State Circuits Yung-Hui Chung, Jieh-Tsorng Wu
2010	—	`conf`	ADC clock jitter measurement and correction using a stochastic TDC. APCCAS Chi-Wei Fan, Jieh-Tsorng Wu
2009	J	`jnl`	A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection. IEEE Trans. Circuits Syst. I Regul. Pap. Chung-Yi Wang, Jieh-Tsorng Wu
2009	J	`jnl`	Jitter Measurement and Compensation for Analog-to-Digital Converters. IEEE Trans. Instrum. Meas. Chi-Wei Fan, Jieh-Tsorng Wu
2007	J	`jnl`	A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration. IEEE J. Solid State Circuits Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu
2007	J	`jnl`	A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Jen-Lin Fan, Chung-Yi Wang, Jieh-Tsorng Wu
2006	—	`conf`	A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration. CICC Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu
2006	J	`jnl`	A background timing-skew calibration technique for time-interleaved analog-to-digital converters. IEEE Trans. Circuits Syst. II Express Briefs Chung-Yi Wang, Jieh-Tsorng Wu
2006	J	`jnl`	Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation. IEEE Trans. Circuits Syst. I Regul. Pap. Ju-Ming Chou, Yu-Tang Hsieh, Jieh-Tsorng Wu
2005	J	`jnl`	A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE J. Solid State Circuits Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu
2005	J	`jnl`	A background comparator calibration technique for flash analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. Chun-Cheng Huang, Jieh-Tsorng Wu
2005	—	`conf`	A robust background calibration technique for switched-capacitor pipelined ADCs. ISCAS (2) Jen-Lin Fan, Jieh-Tsorng Wu
2005	J	`jnl`	Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration". IEEE J. Solid State Circuits Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu
2004	—	`conf`	A statistical background calibration technique for flash analog-to-digital converters. ISCAS (1) Chun-Cheng Huang, Jieh-Tsorng Wu
2004	—	`conf`	Multi-level memory systems using error control codes. ISCAS (2) Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang
2003	—	`conf`	A digital background calibration technique for pipelined analog-to-digital converters. ISCAS (1) Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu
2003	J	`jnl`	A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier. IEEE J. Solid State Circuits Cheng-Chung Hsu, Jieh-Tsorng Wu
2001	—	`conf`	Highly linear 100 MHz CMOS programmable gain amplifiers. ISCAS (1) Cheng-Chung Hsu, Jieh-Tsorng Wu
1999	J	`jnl`	A 2-V, 1.8-GHz BJT phase-locked loop. IEEE J. Solid State Circuits Wei-Zen Chen, Jieh-Tsorng Wu
1998	—	`conf`	A 2 V 1.6 GHz BJT phase-locked loop. CICC Wei-Zen Chen, Jieh-Tsorng Wu
1998	J	`jnl`	A 2-V 2-GHz BJT variable frequency oscillator. IEEE J. Solid State Circuits Wei-Zen Chen, Jieh-Tsorng Wu
1998	J	`jnl`	MOS charge pumps for low-voltage operation. IEEE J. Solid State Circuits Jieh-Tsorng Wu, Kuen-Long Chang
1992	J	`jnl`	A two-chip 1.5-GBd serial link interface. IEEE J. Solid State Circuits Richard C. Walker, Cheryl L. Stout, Jieh-Tsorng Wu, Benny Lai, Chu-Sun Yen, Thomas Hornak, Patrick T. Petruno
1988	J	`jnl`	A 100-MHz pipelined CMOS comparator. IEEE J. Solid State Circuits Jieh-Tsorng Wu, Bruce A. Wooley