Jie Zhou

29 papers A 1B 4C 2Misc 1Journal 10Unranked 11
YearRankTypeTitle / Venue / Authors
2016 B conf
Hyperspectral image classification via kernel extreme learning machine using local receptive fields.
ICIP
Qi Lv, Xin Niu, Yong Dou, Yueqing Wang, Jiaqing Xu, Jie Zhou
2014 J jnl
CuSora: Real-time software radio using multi-core graphics processing unit.
J. Syst. Archit.
Rongchun Li, Yong Dou, Jie Zhou, Lin Deng, Shi Wang
2014 J jnl
Design and Implement of High Performance Crypto Coprocessor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shi-Ce Ni, Yong Dou, Kai Chen, Jie Zhou
2014 J jnl
Efficient Parallel Interference Cancellation MIMO Detector for Software Defined Radio on GPUs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Rongchun Li, Yong Dou, Jie Zhou, Chen Chen
2014 J jnl
Transpose-free variable-size FFT accelerator based on-chip SRAM.
IEICE Electron. Express
Lei Guo, Yuhua Tang, Yuanwu Lei, Yong Dou, Jie Zhou
2013 — conf
A multi-standard efficient column-layered LDPC decoder for Software Defined Radio on GPUs.
SPAWC
Rongchun Li, Jie Zhou, Yong Dou, Song Guo, Dan Zou, Shi Wang
2013 J jnl
FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic.
J. Supercomput.
Yuanwu Lei, Yong Dou, Yazhuo Dong, Jie Zhou, Fei Xia
2013 J jnl
From WiFi to WiMAX: Efficient GPU-based Parameterized Transceiver across Different OFDM Protocols.
KSII Trans. Internet Inf. Syst.
Rongchun Li, Yong Dou, Jie Zhou, Baofeng Li, Jinbo Xu
2013 J jnl
VLIW coprocessor for IEEE-754 quadruple-precision elementary functions.
ACM Trans. Archit. Code Optim.
Yuanwu Lei, Yong Dou, Lei Guo, Jinbo Xu, Jie Zhou, Yazhuo Dong, Hongjian Li
2013 J jnl
Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access.
IEICE Trans. Inf. Syst.
Lei Guo, Yuhua Tang, Yong Dou, Yuanwu Lei, Meng Ma, Jie Zhou
2012 — conf
A malicious code detection method based on statistical analysis.
FSKD
Yunlong Wu, Chen Chen, Huiquan Wang, Jie Zhou, Xinhai Xu
2012 B conf
A self-organizing and self-adaptive French flag Organism based on lateral activation model.
IEEE Congress on Evolutionary Computation
Jiaqing Xu, Qi Lv, Jie Zhou, Yong Dou
2011 — conf
A high-throughput reconfigurable Viterbi decoder.
WCSP
Rongchun Li, Yong Dou, Jie Zhou, Guo-Qing Lei
2011 — conf
FPGA Implementation of Variable-Precision Floating-Point Arithmetic.
APPT
Yuanwu Lei, Yong Dou, Song Guo, Jie Zhou
2011 J jnl
FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic.
IEICE Trans. Inf. Syst.
Yuanwu Lei, Yong Dou, Jie Zhou
2011 C conf
Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA.
ICCD
Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo
2011 B conf
VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic.
FPL
Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang
2010 J jnl
A Unified Co-Processor Architecture for Matrix Decomposition.
J. Comput. Sci. Technol.
Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni
2010 A conf
FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.
ICS
Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen
2009 — conf
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA.
APPT
Jie Zhou, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang
2009 Misc conf
A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs.
FCCM
Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang
2009 B conf
FPGA accelerating three QR decomposition algorithms in the unified pipelined framework.
FPL
Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu
2008 C conf
Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.
HPCC
Jie Zhou, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong
2008 — conf
Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA.
ICESS
Jie Zhou, Yazhuo Dong, Yong Dou, Yuanwu Lei
2008 — conf
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.
ARC
Jie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong
2008 — conf
Multi-access memory architecture for image applications with multiple interested regions.
APCCAS
Jinbo Xu, Yong Dou, Jie Zhou
2008 — conf
Rectangularly Multi-Module Memory System with Table-Based Dynamic Addressing Scheme.
NAS
Jinbo Xu, Yong Dou, Jie Zhou
2007 — conf
FPGA SAR Processor with Window Memory Accesses.
ASAP
Yong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou
2007 — conf
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.
ARC
Yazhuo Dong, Yong Dou, Jie Zhou