Jie Zhang

17 papers A* 4A 6Journal 7
YearRankTypeTitle / Venue / Authors
2015 J jnl
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra
2015 J jnl
Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.
CoRR
Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra
2014 J jnl
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
ACM J. Emerg. Technol. Comput. Syst.
Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, Giovanni De Micheli
2013 A conf
Carbon nanotube circuits: opportunities and challenges.
DATE
Hai Wei, Max M. Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra
2013 A* conf
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations.
DAC
Gage Hills, Jie Zhang, Charles Mackin, Max M. Shulaker, Hai Wei, H.-S. Philip Wong, Subhasish Mitra
2012 J jnl
Carbon Nanotube Robust Digital VLSI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra
2011 A conf
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.
ICCAD
Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra
2011 J jnl
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra
2011 J jnl
Robust System Design.
IPSJ Trans. Syst. LSI Des. Methodol.
Subhasish Mitra, Hyungmin Cho, Ted Hong, Young Moon Kim, Hsiao-Heng Lee, Larkhoon Leem, Yanjing Li, David Lin, Evelyn Mintarno, Diana Mui, Sung-Boem Park, Nishant Patil, Hai Wei, Jie Zhang
2010 A conf
Carbon nanotube circuits: Living with imperfections and variations.
DATE
Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra
2010 A* conf
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
DAC
Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra
2009 A* conf
Carbon nanotube circuits in the presence of carbon nanotube density variations.
DAC
Jie Zhang, Nishant Patil, Arash Hazeghi, Subhasish Mitra
2009 A conf
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.
DATE
Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli
2009 A* conf
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
DAC
Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra
2009 A conf
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.
DATE
Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei
2009 J jnl
Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jie Zhang, Nishant Patil, Subhasish Mitra
2008 A conf
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
DATE
Jie Zhang, Nishant Patil, Subhasish Mitra