Jie Wang - RankMe

40 papers A* 5A 15Misc 4Journal 14Unranked 1

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	PipeRAG: Fast Retrieval-Augmented Generation via Adaptive Pipeline Parallelism. KDD (1) Wenqi Jiang, Shuai Zhang, Boran Han, Jie Wang, Bernie Wang, Tim Kraska
2025	A*	`conf`	Scaling Llama 3 Training with Efficient Parallelism Strategies. ISCA Weiwei Chu, Xinfeng Xie, Jiecao Yu, Jie Wang, Amar Phanishayee, Chunqiang Tang, Yuchen Hao, Jianyu Huang, Mustafa Ozdal, Jun Wang, Vedanuj Goswami, Naman Goyal, Abhishek Kadian, Andrew Gu, Chris Cai, Feng Tian, Xiaodong Wang, Min Si, Pavan Balaji, Ching-Hsiang Chu, Jongsoo Park
2025	A*	`conf`	WLB-LLM: Workload-Balanced 4D Parallelism for Large Language Model Training. OSDI Zheng Wang, Anna Cai, Xinfeng Xie, Zaifeng Pan, Yue Guan, Weiwei Chu, Jie Wang, Shikai Li, Jianyu Huang, Chris Cai, Yuchen Hao, Yufei Ding
2025	J	`jnl`	WLB-LLM: Workload-Balanced 4D Parallelism for Large Language Model Training. CoRR Zheng Wang, Anna Cai, Xinfeng Xie, Zaifeng Pan, Yue Guan, Weiwei Chu, Jie Wang, Shikai Li, Jianyu Huang, Chris Cai, Yuchen Hao, Yufei Ding
2024	J	`jnl`	PipeRAG: Fast Retrieval-Augmented Generation via Algorithm-System Co-design. CoRR Wenqi Jiang, Shuai Zhang, Boran Han, Jie Wang, Bernie Wang, Tim Kraska
2023	A*	`conf`	A Comprehensive Automated Exploration Framework for Systolic Array Designs. DAC Suhail Basalama, Jie Wang, Jason Cong
2023	J	`jnl`	Democratizing Domain-Specific Computing. Commun. ACM Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2023	J	`jnl`	FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. ACM Trans. Reconfigurable Technol. Syst. Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Licheng Guo, Jason Cong
2023	A*	`conf`	Grape: Practical and Efficient Graphed Execution for Dynamic Deep Neural Networks on GPUs. MICRO Bojian Zheng, Cody Hao Yu, Jie Wang, Yaoyao Ding, Yizhi Liu, Yida Wang, Gennady Pekhimenko
2023	J	`jnl`	RAF: Holistic Compilation for Deep Learning Model Training. CoRR Cody Hao Yu, Haozheng Fan, Guangtai Huang, Zhen Jia, Yizhi Liu, Jie Wang, Zach Zheng, Yuan Zhou, Haichen Shen, Junru Shao, Mu Li, Yida Wang
2023	J	`jnl`	TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
2022	Misc	`conf`	A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. FCCM Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2022	J	`jnl`	Democratizing Domain-Specific Computing. CoRR Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2022	A	`conf`	RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2022	J	`jnl`	TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
2021	A	`conf`	AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong
2021	A	`conf`	AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. FPGA Jie Wang, Licheng Guo, Jason Cong
2021	—	`—`	Automatic Synthesis and Architecture Optimization of Systolic Arrays. Jie Wang
2021	Misc	`conf`	Extending High-Level Synthesis for Task-Parallel Programs. FCCM Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong
2021	A	`conf`	Extending High-Level Synthesis for Task-Parallel Programs. FPGA Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong
2021	A	`conf`	MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. FPGA Peipei Zhou, Jiayi Sheng, Cody Hao Yu, Peng Wei, Jie Wang, Di Wu, Jason Cong
2021	J	`jnl`	Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned. CoRR Jie Wang, Jason Cong
2021	A	`conf`	UNIT: Unifying Tensorized Instruction Compilation. CGO Jian Weng, Animesh Jain, Jie Wang, Leyuan Wang, Yida Wang, Tony Nowatzki
2021	J	`jnl`	UNIT: Unifying Tensorized Instruction Compilation. CoRR Jian Weng, Animesh Jain, Jie Wang, Leyuan Wang, Yida Wang, Tony Nowatzki
2020	Misc	`conf`	Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. FCCM Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang, Jason Cong
2020	A*	`conf`	Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
2020	A	`conf`	Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
2020	A	`conf`	End-to-End Optimization of Deep Learning Applications. FPGA Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2020	J	`jnl`	Extending High-Level Synthesis for Task-Parallel Programs. CoRR Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong
2020	J	`jnl`	FLASH: Fast, Parallel, and Accurate Simulator for HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Young-kyu Choi, Yuze Chi, Jie Wang, Jason Cong
2020	A	`conf`	SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey
2020	J	`jnl`	When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. CoRR Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong
2019	A	`conf`	HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
2019	A	`conf`	Rapid Cycle-Accurate Simulator for High-Level Synthesis. FPGA Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
2018	Misc	`conf`	Automatic Interior I/O Elimination in Systolic Array Architecture. FCCM Jason Cong, Jie Wang
2018	A	`conf`	PolySA: polyhedral-based systolic array auto-compilation. ICCAD Jason Cong, Jie Wang
2018	J	`jnl`	Rapid Cycle-Accurate Simulator for High-Level Synthesis. CoRR Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
2017	A	`conf`	Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms. IPDPS Jie Wang, Xinfeng Xie, Jason Cong
2016	A	`conf`	Going Deeper with Embedded FPGA Platform for Convolutional Neural Network. FPGA Jiantao Qiu, Jie Wang, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang, Ningyi Xu, Sen Song, Yu Wang, Huazhong Yang
2015	A	`conf`	Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only). FPGA Jie Wang, Jason Cong