Jie S. Hu

35 papers A* 2A 6C 1Journal 13Unranked 13
YearRankTypeTitle / Venue / Authors
2012 J jnl
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures.
IET Comput. Digit. Tech.
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2012 — conf
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors.
DFT
Chuanlei Zheng, Parijat Shukla, Shuai Wang, Jie S. Hu
2012 J jnl
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2011 — conf
Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors.
ISVLSI
Li Tang, Shuai Wang, Jie S. Hu, Xiaobo Sharon Hu
2010 J jnl
On the Thermal Attack in Instruction Caches.
IEEE Trans. Dependable Secur. Comput.
Joonho Kong, Johnsy K. John, Eui-Young Chung, Sung Woo Chung, Jie S. Hu
2010 — conf
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array.
ISVLSI
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2009 J jnl
Compiler-assisted soft error detection under performance and energy constraints in embedded systems.
ACM Trans. Embed. Comput. Syst.
Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2009 A conf
Exploiting narrow-width values for thermal-aware register file designs.
DATE
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung
2009 J jnl
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors.
IEEE Trans. Computers
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2009 J jnl
On the Exploitation of Narrow-Width Values for Improving Register File Reliability.
IEEE Trans. Very Large Scale Integr. Syst.
Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
2008 J jnl
Asymmetrically banked value-aware register files for low-energy and high-performance.
Microprocess. Microsystems
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
2008 — conf
BTB Access Filtering: A Low Energy and High Performance Design.
ISVLSI
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2008 J jnl
Self-Adaptive Data Caches for Soft-Error Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2007 — conf
Asymmetrically Banked Value-Aware Register Files.
ISVLSI
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
2007 — conf
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors.
ERSA
Xiaofang Wang, Sotirios G. Ziavras, Jie S. Hu
2007 — conf
FPGA-based Vector Processing for Matrix Operations.
ITNG
Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu
2007 J jnl
Optimising power efficiency in trace cache fetch unit.
IET Comput. Digit. Tech.
Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
2007 J jnl
Reconfiguration support for vector operations.
Int. J. High Perform. Syst. Archit.
Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu
2007 — conf
Vector Processing Support for FPGA-Oriented High Performance Applications.
ISVLSI
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu
2006 A conf
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.
DSN
Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
2006 — conf
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.
ICSAMOS
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2005 J jnl
Analyzing data reuse for cache reconfiguration.
ACM Trans. Embed. Comput. Syst.
Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2005 A conf
Compiler-Directed Instruction Duplication for Soft Error Detection.
DATE
Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2005 C conf
Optimizing the Thermal Behavior of Subarrayed Data Caches.
ICCD
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
2005 — conf
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures.
Asia-Pacific Computer Systems Architecture Conference
Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras
2004 A* conf
Exploring Wakeup-Free Instruction Scheduling.
HPCA
Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin
2004 J jnl
Reducing instruction cache energy consumption using a compiler-based strategy.
ACM Trans. Archit. Code Optim.
Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2004 A conf
Scheduling Reusable Instructions for Power Reduction.
DATE
Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin
2003 A conf
Exploiting program hotspots and code sequentiality for instruction cache leakage management.
ISLPED
Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
2003 J jnl
Leakage Current: Moore's Law Meets Static Power.
Computer
Nam Sung Kim, Todd M. Austin, David T. Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan
2003 — conf
Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch.
ISVLSI
Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
2002 — conf
Compiler-directed cache polymorphism.
LCTES-SCOPES
Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang
2002 A* conf
Compiler-directed instruction cache leakage optimization.
MICRO
Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2002 — conf
Energy-conscious compilation based on voltage scaling.
LCTES-SCOPES
Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer
2002 A conf
Power-Efficient Trace Caches.
DATE
Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin