Jie Li

20 papers C 1Journal 11Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
Error Correction Codes for Double Burst Errors Correction in Memories.
IEEE Access
He Liu, Liyi Xiao, Tianqi Wang, Jiaqiang Li, Jie Li
2024 J jnl
SET-detection low complexity burst error correction codes for SRAM protection.
Integr.
He Liu, Jiaqiang Li, Liyi Xiao, Tianqi Wang, Jie Li
2022 J jnl
A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang
2022 J jnl
A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors.
IEEE Access
Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang
2021 J jnl
Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hongchen Li, Liyi Xiao, Chunhua Qi, Jie Li
2021 J jnl
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH).
Integr.
Jie Li, Pedro Reviriego, Shanshan Liu, Liyi Xiao, Fabrizio Lombardi
2020 J jnl
An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA.
IEEE Trans. Reliab.
Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Linzhe Li
2020 J jnl
Scheme for periodical concurrent fault detection in parallel CRC circuits.
IET Comput. Digit. Tech.
Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi
2019 J jnl
A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuebing Cao, Liyi Xiao, Jie Li, Rongsheng Zhang, Shanshan Liu, Jinxiang Wang
2019 — conf
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network.
ASICON
Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang
2019 — conf
Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology.
ASICON
Hongchen Li, Liyi Xiao, Jie Li, He Liu
2019 — conf
Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs.
ICICDT
Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Tianqi Wang
2019 — conf
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.
ASICON
Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao
2018 J jnl
A fast fault injection platform of multiple SEUs for SRAM-based FPGAs.
Microelectron. Reliab.
Rongsheng Zhang, Liyi Xiao, Jie Li, Xuebing Cao, Chunhua Qi, Jiaqiang Li, Mingjiang Wang
2018 J jnl
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Costas Argyrides, Jie Li
2018 C conf
Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm.
IOLTS
Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Jiaqiang Li, Jinxiang Wang
2017 — conf
A fast and accurate fault injection platform for SRAM-based FPGAs.
ASICON
Rongsheng Zhang, Liyi Xiao, Jie Li
2017 — conf
A method to estimate cross-section of circuits at RTL levels.
ASICON
Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li, Tianqi Wang
2017 — conf
Low redundancy matrix-based codes for adjacent error correction with parity sharing.
ISQED
Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao
2015 — conf
Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories.
ISQED
Liyi Xiao, Jiaqiang Li, Jie Li, Jing Guo