Jie Gu - RankMe

65 papers A* 9A 5C 1Journal 18Unranked 32

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	36.2 A Neural Interface SoC for Smart Glasses with Low-Power Neural Commanding and Efficient LoRA-Enabled On-Chip Learning. ISSCC Zhiwei Zhong, He Yu, William McGarry, Yijie Wei, Jie Gu
2026	A*	`conf`	LLA: Enhancing Security and Privacy for Generative Models with Logic-Locked Accelerators. AAAI You Li, Guannan Zhao, Yuhao Ju, Yunqi He, Jie Gu, Hai Zhou
2026	—	`conf`	Proactive Power Management-Based Supply Regulation with Online Learning for Variation-Tolerant Workload-Aware Droop Mitigation in 28nm CMOS. ISSCC Xi Chen, Andrew Liss, William Covington, Qiankai Cao, Yiqi Li, Kang Wei, Raveesh Magod, Muhammad Khellah, Xin Zhang, Jie Gu
2025	J	`jnl`	A 65 nm General-Purpose Compute-in-Memory Processor Supporting Both General Programming and Deep Learning Tasks. IEEE J. Solid State Circuits Yuhao Ju, Yijie Wei, Jie Gu
2025	J	`jnl`	A 65-nm Humanoid Robot System-on-Chip Using Time-Domain 3-D Footstep Planning and Mixed-Signal ZMP Gait Scheduler With Inverse Kinematics. IEEE J. Solid State Circuits Qiankai Cao, Juin Chuen Oh, Jie Gu
2025	J	`jnl`	A 65-nm Proactive Power Management Technique With Real-Time Machine Learning Engine for Droop Prediction and Mitigation on Microprocessors. IEEE J. Solid State Circuits Xi Chen, Jiaxiang Feng, Aly Shoukry, Xin Zhang, Raveesh Magod, Nachiket V. Desai, Jie Gu
2025	—	`conf`	Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR Applications. ASP-DAC Zhiwei Zhong, Yijie Wei, Lance Christopher Go, Yiqi Li, Jie Gu
2025	—	`conf`	Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse Kinematics. ASP-DAC Qiankai Cao, Yiqi Li, Juin Chuen Oh, Jie Gu
2025	J	`jnl`	LLA: Enhancing Security and Privacy for Generative Models with Logic-Locked Accelerators. CoRR You Li, Guannan Zhao, Yuhao Ju, Yunqi He, Jie Gu, Hai Zhou
2025	J	`jnl`	Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering. IEEE J. Solid State Circuits Shiyu Guo, Yuhao Ju, Xi Chen, Sachin S. Sapatnekar, Jie Gu
2025	—	`conf`	Modeling, Design and In-situ Demonstration of Bio-inspired Central Pattern Generator and Neuromorphic Computing Circuits for Complex Kinematic Control of Quadruped Robots. ACM Great Lakes Symposium on VLSI Qiankai Cao, Yuhao Ju, Zhiwei Zhong, Zhengyu Chen, Jie Gu
2024	—	`conf`	20.4 A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices. ISSCC Yuhao Ju, Ganqi Xu, Jie Gu
2024	—	`conf`	33.2 A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture. ISSCC Zhiwei Zhong, Yijie Wei, Lance Christopher Go, Jie Gu
2024	—	`conf`	A Mixed-signal 3D Footstep Planning SoC for Motion Control of Humanoid Robots with Embedded Zero-Moment-Point based Gait Scheduler and Neural Inverse Kinematics. VLSI Technology and Circuits Qiankai Cao, Juin Chuen Oh, Jie Gu
2024	A*	`conf`	LLM-MARK: A Computing Framework on Efficient Watermarking of Large Language Models for Authentic Use of Generative AI at Local Devices. DAC Shiyu Guo, Yuhao Ju, Xi Chen, Jie Gu
2024	—	`conf`	Scalable Physics-Embedded Neural Networks for Real-Time Robotic Control in Embedded Systems. MWSCAS Zhiwei Zhong, Yuhao Ju, Jie Gu
2024	—	`conf`	Software-Hardware Codesign of Ray-Tracing Accelerator for Edge AR/VR With Viewpoint-Focused 3D Construction and Efficient Data Structure. MWSCAS Shiyu Guo, Sachin S. Sapatnekar, Jie Gu
2023	—	`conf`	A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking. CICC Xi Chen, Aly Shoukry, Tianyu Jia, Xin Zhang, Raveesh Magod, Nachiket V. Desai, Jie Gu
2023	—	`conf`	A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality. VLSI Technology and Circuits Yuhao Ju, Yijie Wei, Xi Chen, Jie Gu
2023	J	`jnl`	A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance. IEEE J. Solid State Circuits Yuhao Ju, Jie Gu
2023	A	`conf`	Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning. ISLPED Qiankai Cao, Xi Chen, Jie Gu
2023	—	`conf`	Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration. VLSI Technology and Circuits Yijie Wei, Xi Chen, Jie Gu
2023	—	`conf`	Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs. VLSI Technology and Circuits Xi Chen, Jiaxiang Feng, Aly Shoukry, Xin Zhang, Raveesh Magod, Nachiket V. Desai, Jie Gu
2022	—	`conf`	A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition. CICC Yijie Wei, Xi Chen, Jie Gu
2022	—	`conf`	A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance. ISSCC Yuhao Ju, Jie Gu
2022	—	`conf`	A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement. ESSCIRC Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu
2022	—	`conf`	A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management. VLSI Technology and Circuits Qiankai Cao, Jie Gu
2022	A*	`conf`	Human emotion based real-time memory and computation management on resource-limited edge devices. DAC Yijie Wei, Zhiwei Zhong, Jie Gu
2021	—	`conf`	15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency. ISSCC Zhengyu Chen, Xi Chen, Jie Gu
2021	J	`jnl`	A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique. IEEE J. Solid State Circuits Tianyu Jia, Yuhao Ju, Jie Gu
2021	J	`jnl`	A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier. IEEE J. Solid State Circuits Yijie Wei, Qiankai Cao, Kofi Otseidu, Levi J. Hargrove, Jie Gu
2021	J	`jnl`	High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. IEEE J. Solid State Circuits Zhengyu Chen, Jie Gu
2021	J	`jnl`	Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. IACR Cryptol. ePrint Arch. Amin Rezaei, Jie Gu, Hai Zhou
2020	—	`conf`	31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators. ISSCC Tianyu Jia, Yuhao Ju, Jie Gu
2020	—	`conf`	A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training. CICC Yijie Wei, Qiankai Cao, Jie Gu, Kofi Otseidu, Levi J. Hargrove
2020	—	`conf`	A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. VLSI Circuits Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu
2020	—	`conf`	A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication. EMBC Yijie Wei, Qiankai Cao, Levi J. Hargrove, Jie Gu
2020	J	`jnl`	An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. IEEE J. Solid State Circuits Tianyu Jia, Yijie Wei, Russ Joseph, Jie Gu
2020	A*	`conf`	Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC. DAC Yijie Wei, Kofi Otseidu, Jie Gu
2020	A*	`conf`	NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. MICRO Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu
2019	—	`conf`	A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. ISSCC Zhengyu Chen, Jie Gu
2019	J	`jnl`	A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation. IEEE J. Solid State Circuits Zhengyu Chen, Jie Gu
2019	—	`conf`	An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. ISSCC Tianyu Jia, Russ Joseph, Jie Gu
2019	J	`jnl`	An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. IEEE J. Solid State Circuits Tianyu Jia, Russ Joseph, Jie Gu
2019	A*	`conf`	Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. DAC Zhengyu Chen, Hai Zhou, Jie Gu
2019	—	`conf`	Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. ISVLSI Amin Rezaei, Jie Gu, Hi Zhou
2019	J	`jnl`	R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. IEEE Trans. Very Large Scale Integr. Syst. Zhengyu Chen, Hai Zhou, Jie Gu
2018	J	`jnl`	A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. IEEE Trans. Very Large Scale Integr. Syst. Zhengyu Chen, Huanyu Wang, Geng Xie, Jie Gu
2018	J	`jnl`	A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications. IEEE J. Solid State Circuits Tianyu Jia, Jie Gu
2018	—	`conf`	A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications. A-SSCC Tianyu Jia, Jie Gu
2018	—	`conf`	An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. A-SSCC Zhengyu Chen, Jie Gu
2018	—	`conf`	An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC Tianyu Jia, Russ Joseph, Jie Gu
2018	A*	`conf`	Compiler-guided instruction-level clock scheduling for timing speculative processors. DAC Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph
2018	A	`conf`	Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. DATE Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou
2018	J	`jnl`	Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design. IEEE Trans. Very Large Scale Integr. Syst. Shuyu Kong, Hai Zhou, Jie Gu
2018	A	`conf`	Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion. ICCAD Kofi Otseidu, Tianyu Jia, Joshua Bryne, Levi J. Hargrove, Jie Gu
2018	—	`conf`	Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs. SoCC Josiah D. Hester, Tianyu Jia, Jie Gu
2018	C	`conf`	R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. ICCD Zhengyu Chen, Hai Zhou, Jie Gu
2017	—	`conf`	(Invited) Software-guided greybox design methodology with integrated power and clock management. MWSCAS Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu
2017	J	`jnl`	Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks. IACR Cryptol. ePrint Arch. Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou
2017	A*	`conf`	Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. DAC Tianyu Jia, Russ Joseph, Jie Gu
2017	—	`conf`	Memristor-Based Clock Design and Optimization with In-Situ Tunability. ISVLSI Shuyu Kong, Jie Gu, Hai Zhou
2016	A	`conf`	Analysis and Design of Energy Efficient Time Domain Signal Processing. ISLPED Zhengyu Chen, Jie Gu
2016	A	`conf`	Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design. ISLPED Huanyu Wang, Geng Xie, Jie Gu
2016	A*	`conf`	Exploration of associative power management with instruction governed operation for ultra-low power design. DAC Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu