Jie-Hong R. Jiang

101 papers A* 31A 27C 1Misc 3Journal 24Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Error-Tolerant Quantum State Discrimination: Optimization and Quantum Circuit Synthesis. TACAS (2) Chien-Kai Ma, Bo-Hung Chen, Tian-Fu Chen, Dah-Wei Chiou, Jie-Hong R. Jiang
2026	—	`conf`	Formalization of Rectification Learning for Economic Design Updates. ASP-DAC Victor N. Kravets, Jie-Hong R. Jiang
2025	A	`conf`	GradMap: A Gradient-Descent Approach to Simultaneous Technology Mapping, Buffer Insertion, and Gate Sizing. ICCAD Hsin-Ying Tsai, Chung-Kai Wu, Chih-Cheng Hsu, Jie-Hong R. Jiang
2025	—	`conf`	SliQSim: A Quantum Circuit Simulator and Solver for Probability and Statistics Queries. TACAS (3) Tian-Fu Chen, Jie-Hong R. Jiang
2025	A	`conf`	Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization. ICCAD Jiun-Hao Chen, Jie-Hong R. Jiang, Alan Mishchenko
2024	Misc	`conf`	A Holistic Approach to Rotation Synthesis for Fault- Tolerant Quantum Computation. QCE Tian-Fu Chen, Cheng-Han Liu, Jie-Hong R. Jiang
2024	A*	`conf`	Knowledge Compilation for Incremental and Checkable Stochastic Boolean Satisfiability. IJCAI Che Cheng, Yun-Rong Luo, Jie-Hong R. Jiang
2024	A*	`conf`	Unifying Decision and Function Queries in Stochastic Boolean Satisfiability. AAAI Yu-Wei Fan, Jie-Hong R. Jiang
2023	J	`jnl`	A Resolution Proof System for Dependency Stochastic Boolean Satisfiability. J. Autom. Reason. Yun-Rong Luo, Che Cheng, Jie-Hong R. Jiang
2023	J	`jnl`	Circuit Learning: From Decision Trees to Decision Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Shan Huang, Jie-Hong R. Jiang
2023	A*	`conf`	Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration. DAC Chun-Yu Wei, Jie-Hong R. Jiang
2023	A*	`conf`	Lifting (D)QBF Preprocessing and Solving Techniques to (D)SSAT. AAAI Che Cheng, Jie-Hong R. Jiang
2023	J	`jnl`	Quantized Neural Network Synthesis for Direct Logic Circuit Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Shan Huang, Jie-Hong R. Jiang, Alan Mishchenko
2023	A*	`conf`	Second-Order Quantified Boolean Logic. AAAI Jie-Hong R. Jiang
2023	A*	`conf`	SharpSSAT: A Witness-Generating Stochastic Boolean Satisfiability Solver. AAAI Yu-Wei Fan, Jie-Hong R. Jiang
2023	Misc	`conf`	VanQiRA: A Vanishing-State-Based Framework for Quantum Circuit Runtime Assertion. QCE Tian-Fu Chen, Chun-Yu Wei, Jie-Hong R. Jiang
2023	A	`conf`	WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits. ICCAD Kuo-Wei Ho, Shao-Ting Chung, Tian-Fu Chen, Yu-Wei Fan, Che Cheng, Cheng-Han Liu, Jie-Hong R. Jiang
2022	A*	`conf`	Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification. DAC Chun-Yu Wei, Yuan-Hung Tsai, Chiao-Shan Jhang, Jie-Hong R. Jiang
2022	J	`jnl`	Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective. IEEE J. Emerg. Sel. Topics Circuits Syst. Giovanni De Micheli, Jie-Hong R. Jiang, Robert Rand, Kaitlin N. Smith, Mathias Soeken
2022	J	`jnl`	Design and Automation for Quantum Computation and Quantum Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. Jie-Hong R. Jiang, Giovanni De Micheli, Kaitlin N. Smith, Mathias Soeken
2022	A*	`conf`	Encoding Probabilistic Graphical Models into Stochastic Boolean Satisfiability. IJCAI Cheng-Han Hsieh, Jie-Hong R. Jiang
2022	J	`jnl`	Homing Sequence Derivation With Quantified Boolean Satisfiability. IEEE Trans. Computers Kuan-Hua Tu, Hung-En Wang, Jie-Hong R. Jiang, Natalia Kushik, Nina Yevtushenko
2022	A	`conf`	Language Equation Solving via Boolean Automata Manipulation. ICCAD Wan-Hsuan Lin, Chia-Hsuan Su, Jie-Hong R. Jiang
2022	J	`jnl`	Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chia-Chih Chi, Jie-Hong R. Jiang
2022	Misc	`conf`	Partial Equivalence Checking of Quantum Circuits. QCE Tian-Fu Chen, Jie-Hong R. Jiang, Min-Hsiu Hsieh
2022	—	`conf`	Reconfigurable Biochemical Circuit Synthesis from Biomachine Specification. BioCAS Chang-Jun Wang, Jie-Hong R. Jiang
2021	A	`conf`	A Circuit-Based SAT Solver for Logic Synthesis. ICCAD He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko
2021	A*	`conf`	A Sharp Leap from Quantified Boolean Formula to Stochastic Boolean Satisfiability Solving. AAAI Pei-Wei Chen, Yu-Ching Huang, Jie-Hong R. Jiang
2021	A*	`conf`	Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation. DAC Yuan-Hung Tsai, Jie-Hong R. Jiang, Chiao-Shan Jhang
2021	J	`jnl`	Constraint Solving for Synthesis and Verification of Threshold Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nian-Ze Lee, Jie-Hong R. Jiang
2021	A*	`conf`	Deep Integration of Circuit Simulator and SAT Solver. DAC He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton
2021	A*	`conf`	Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty. AAAI Nian-Ze Lee, Jie-Hong R. Jiang
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	J	`jnl`	SAT-Based On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang
2020	J	`jnl`	Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation to a New Level. CoRR Yuan-Hung Tsai, Jie-Hong R. Jiang, Chiao-Shan Jhang
2020	A	`conf`	Engineering Change Order for Combinational and Sequential Design Rectification. DATE Jie-Hong R. Jiang, Victor N. Kravets, Nian-Ze Lee
2020	A	`conf`	Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle. DATE Victor N. Kravets, Jie-Hong R. Jiang, Heinz Riener
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2020	A	`conf`	Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning. ICCAD Yu-Chou Lin, Jie-Hong R. Jiang
2020	A*	`conf`	SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies. DAC He-Teng Zhang, Jie-Hong R. Jiang
2020	A	`conf`	Symbolic Uniform Sampling with XOR Circuits. ICCAD Yen-Ting Lin, Jie-Hong R. Jiang, Victor N. Kravets
2020	A*	`conf`	Time Multiplexing via Circuit Folding. DAC Po-Chun Chien, Jie-Hong R. Jiang
2019	A	`conf`	A Cube Distribution Approach to QBF Solving and Certificate Minimization. CP Li-Cheng Chen, Jie-Hong R. Jiang
2019	—	`conf`	An approximation algorithm to the optimal switch control of reconfigurable battery packs. ASP-DAC Shih-Yu Chen, Jie-Hong R. Jiang, Shou-Hung Welkin Ling, Shih-Hao Liang, Mao-Cheng Huang
2019	A*	`conf`	Comprehensive Search for ECO Rectification Using Symbolic Sampling. DAC Victor N. Kravets, Nian-Ze Lee, Jie-Hong R. Jiang
2019	J	`jnl`	Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty. CoRR Nian-Ze Lee, Jie-Hong R. Jiang
2019	A*	`conf`	Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis. DAC Hao Chen, Shao-Chun Hung, Jie-Hong R. Jiang
2019	—	`conf`	Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. ASYNC Yi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang
2019	A	`conf`	Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. ICCAD Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang
2019	A	`conf`	Time-Frame Folding: Back to the Sequentiality. ICCAD Po-Chun Chien, Jie-Hong R. Jiang
2018	A*	`conf`	A symbolic model checking approach to the analysis of string and length constraints. ASE Hung-En Wang, Shih-Yu Chen, Fang Yu, Jie-Hong R. Jiang
2018	A	`conf`	Canonicalization of threshold logic representation and its applications. ICCAD Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang
2018	A*	`conf`	Cost-aware patch generation for multi-target function rectification of engineering change orders. DAC He-Teng Zhang, Jie-Hong R. Jiang
2018	A*	`conf`	Efficient computation of ECO patch functions. DAC Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton
2018	A	`conf`	Logic synthesis of binarized neural networks for efficient circuit implementation. ICCAD Chia-Chih Chi, Jie-Hong R. Jiang
2018	A*	`conf`	Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection. IJCAI Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang
2018	J	`jnl`	Towards Formal Evaluation and Verification of Probabilistic Design. IEEE Trans. Computers Nian-Ze Lee, Jie-Hong R. Jiang
2017	J	`jnl`	A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiao-Lei Chien, Mei-Yen Chiu, Jie-Hong R. Jiang
2017	A*	`conf`	Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits. DAC Cheng-Yu Shih, Chun-Hong Shih, Jie-Hong R. Jiang
2017	—	`conf`	Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines. ASYNC Chun-Hong Shih, Jie-Hong R. Jiang
2017	C	`conf`	Homing Sequence Derivation with Quantified Boolean Satisfiability. ICTSS Hung-En Wang, Kuan-Hua Tu, Jie-Hong R. Jiang, Natalia Kushik
2017	A*	`conf`	Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation. DAC Chun-Ning Lai, Jie-Hong R. Jiang
2017	—	`conf`	Recombinase-based genetic circuit optimization. BioCAS Chun-Ning Lai, Jie-Hong R. Jiang, François Fages
2017	A	`conf`	Sequential engineering change order under retiming and resynthesis. ICCAD Nian-Ze Lee, Victor N. Kravets, Jie-Hong R. Jiang
2017	A*	`conf`	Solving Stochastic Boolean Satisfiability under Random-Exist Quantification. IJCAI Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang
2016	A	`conf`	Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. ICCAD Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang
2016	A*	`conf`	Design partitioning for large-scale equivalence checking and functional correction. DAC Grace Wu, Yi-Tin Sun, Jie-Hong R. Jiang
2016	J	`jnl`	Flexibility and Optimization of QBF Skolem-Herbrand Certificates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Valeriy Balabanov, Shuo-Ren Lin, Jie-Hong R. Jiang
2016	J	`jnl`	Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang
2016	J	`jnl`	Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang
2016	—	`conf`	String Analysis via Automata Manipulation with Logic Circuit Representation. CAV (1) Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang
2015	A	`conf`	A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. ICCAD Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang
2015	J	`jnl`	Deriving Compositionally Deadlock-Free Components over Synchronous Automata Compositions. Comput. J. Nina Yevtushenko, Khaled El-Fakih, Tiziano Villa, Jie-Hong R. Jiang
2015	A	`conf`	Property-Directed Synthesis of Reactive Systems from Safety Specifications. ICCAD Ting-Wei Chiang, Jie-Hong R. Jiang
2015	A	`conf`	QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving. SAT Kuan-Hua Tu, Tzu-Chien Hsu, Jie-Hong R. Jiang
2015	—	`conf`	Reconfigurable neuromorphic computation in biochemical systems. EMBC Hui-Ju Katherine Chiang, Jie-Hong R. Jiang, François Fages
2015	A*	`conf`	Scalable sequence-constrained retention register minimization in power gating design. DAC Ting-Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, Jie-Hong R. Jiang
2014	—	`conf`	Building reconfigurable circuitry in a biochemical world. BioCAS Hui-Ju Katherine Chiang, Jie-Hong R. Jiang, François Fages
2014	J	`jnl`	Henkin quantifiers and Boolean formulae: A certification perspective of DQBF. Theor. Comput. Sci. Valeriy Balabanov, Hui-Ju Katherine Chiang, Jie-Hong R. Jiang
2014	A	`conf`	QBF Resolution Systems and Their Proof Complexities. SAT Valeriy Balabanov, Magdalena Widl, Jie-Hong R. Jiang
2014	A*	`conf`	Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. DAC Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang
2014	A*	`conf`	Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. DAC Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang
2014	A	`conf`	Towards formal evaluation and verification of probabilistic design. ICCAD Nian-Ze Lee, Jie-Hong R. Jiang
2013	A	`conf`	Automatic test pattern generation for delay defects using timed characteristic functions. ICCAD Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, Chien-Mo James Li
2013	A	`conf`	Encoding multi-valued functions for symmetry. ICCAD Ko-Lung Yuan, Chien-Yen Kuo, Jie-Hong R. Jiang, Meng-Yen Li
2013	—	`conf`	On the Hybrid Composition and Simulation of Heterogeneous Biochemical Models. CMSB Hui-Ju Katherine Chiang, François Fages, Jie-Hong R. Jiang, Sylvain Soliman
2013	J	`jnl`	Software Workarounds for Hardware Errors: Instruction Patch Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsung-Po Liu, Shuo-Ren Lin, Jie-Hong R. Jiang
2013	A*	`conf`	Synthesis of feedback decoders for initialized encoders. DAC Kuan-Hua Tu, Jie-Hong R. Jiang
2012	J	`jnl`	Automatic Decoder Synthesis: Methods and Case Studies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang
2012	—	`conf`	Clock rescheduling for timing engineering change orders. ASP-DAC Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang
2012	A	`conf`	Compiling program control flows into biochemical reactions. ICCAD De-An Huang, Jie-Hong R. Jiang, Ruei-Yang Huang, Chi-Yun Cheng
2012	J	`jnl`	Unified QBF certification and its applications. Formal Methods Syst. Des. Valeriy Balabanov, Jie-Hong R. Jiang
2011	A*	`conf`	Resolution Proofs and Skolem Functions in QBF Evaluation and Applications. CAV Valeriy Balabanov, Jie-Hong R. Jiang
2011	J	`jnl`	Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang
2011	A	`conf`	Towards completely automatic decoder synthesis. ICCAD Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang
2010	A*	`conf`	BooM: a decision procedure for boolean matching with abstraction and dynamic learning. DAC Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang
2010	A	`conf`	Boolean matching of function vectors with strengthened learning. ICCAD Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang
2010	—	`conf`	TRECO: dynamic technology remapping for timing engineering change orders. ASP-DAC Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang
2009	A*	`conf`	Quantifier Elimination via Functional Composition. CAV Jie-Hong R. Jiang
2007	J	`jnl`	Quantum Mechanical Search and Harmonic Perturbation. Quantum Inf. Process. Jie-Hong R. Jiang, Dah-Wei Chiou, Cheng-En Wu
1997	—	`conf`	BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. ASP-DAC Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei