Jiayi Zhu

15 papers B 2C 4Journal 7Unranked 2
YearRankTypeTitle / Venue / Authors
2017 J jnl
An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.
IEEE J. Solid State Circuits
Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto
2016 — conf
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.
ISSCC
Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto
2015 J jnl
A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Jinjia Zhou, Dajiang Zhou, Jiayi Zhu, Satoshi Goto
2015 C conf
An independent bandwidth reduction device for HEVC VLSI video system.
ISCAS
Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2014 C conf
An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder.
VCIP
Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto
2014 J jnl
Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2014 B conf
Fast SAO estimation algorithm and its VLSI architecture.
ICIP
Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2013 J jnl
A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jiayi Zhu, Dajiang Zhou, Satoshi Goto
2013 B conf
A combined SAO and de-blocking filter architecture for HEVC video decoder.
ICIP
Jiayi Zhu, Dajiang Zhou, Gang He, Satoshi Goto
2012 — conf
A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications.
ISSCC
Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto
2011 J jnl
A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip.
IEEE J. Solid State Circuits
Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto
2010 J jnl
A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder.
IEICE Trans. Electron.
Xianmin Chen, Peilin Liu, Dajiang Zhou, Jiayi Zhu, Xingguang Pan, Satoshi Goto
2009 J jnl
A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Satoshi Goto
2009 C conf
Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder.
ISCAS
Xianmin Chen, Peilin Liu, Jiayi Zhu, Dajiang Zhou, Satoshi Goto
2008 C conf
An SDRAM controller optimized for high definition video coding application.
ISCAS
Jiayi Zhu, Peilin Liu, Dajiang Zhou