Jianyi Meng

33 papers A* 1B 1Journal 24Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
ARV-Q: An Adaptive RISC-V Vector Processor for Unified Support of Post-Quantum Standards and Side-Channel Protection on the Edge.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yifan Zhao, Honglin Kuang, Xinglong Yu, Yi Sun, Ziyi Hao, Jianyi Meng, Jun Han
2023 — conf
Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography.
ASAP
Yifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han
2022 B conf
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.
ICPADS
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
2022 J jnl
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.
CoRR
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
2020 A* conf
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.
ISCA
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
2020 — conf
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V.
Hot Chips Symposium
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi
2019 J jnl
A Granular Resampling Method and Adaptive Speculative Mechanism-Based Energy-Efficient Architecture for Multiclass Heartbeat Classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yin Xu, Zhijian Chen, Feiteng Li, Jianyi Meng
2019 J jnl
SCSE: Boosting Symbolic Execution via State Concretization.
IEICE Trans. Inf. Syst.
Huibin Wang, Chunqiang Li, Jianyi Meng, Xiaoyan Xiang
2018 J jnl
A Cross-layer based mapping for spiking neural network onto network on chip.
Int. J. Parallel Emergent Distributed Syst.
Yande Xiang, Jianyi Meng
2018 J jnl
A Highly Adaptive Lossless ECG Compression ASIC for Wireless Sensors Based on Hybrid Gomlomb Coding.
IEICE Trans. Inf. Syst.
Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng
2018 J jnl
A low power QRS detection processor with adaptive scaling of processing resolution.
IEICE Electron. Express
Zhijian Chen, Menghan Jia, Jiahui Luo, Tao-Tao Zhu, Xiaoyan Xiang, Jianyi Meng
2018 J jnl
An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection.
IEEE Trans. Circuits Syst. II Express Briefs
Zhijian Chen, Jiahui Luo, Kaiwen Lin, Jiaquan Wu, Tao-Tao Zhu, Xiaoyan Xiang, Jianyi Meng
2018 J jnl
An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs.
IEICE Electron. Express
Yan He, Jianyi Meng, Zhijian Chen, Xiaoyan Xiang, Chen Chen
2018 J jnl
An energy-efficient parallel VLSI architecture for SVM classification.
IEICE Electron. Express
Yin Xu, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng
2018 J jnl
ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference.
IEICE Trans. Inf. Syst.
Yande Xiang, Jiahui Luo, Tao-Tao Zhu, Sheng Wang, Xiaoyan Xiang, Jianyi Meng
2018 J jnl
Low-power perceptron model based ECG processor for premature ventricular contraction detection.
Microprocess. Microsystems
Zhijian Chen, Huanzhang Xu, Jiahui Luo, Tao-Tao Zhu, Jianyi Meng
2018 J jnl
Relative ordering learning in spiking neural network for pattern recognition.
Neurocomputing
Zhitao Lin, De Ma, Jianyi Meng, Linna Chen
2017 J jnl
A dual-mode ECG processor with difference-insensitive QRS detection and lossless compression.
IEICE Electron. Express
Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng, Haibin Shen
2017 J jnl
A granular resampling method based energy-efficient architecture for heartbeat classification in ECG.
IEICE Electron. Express
Yin Xu, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng
2017 J jnl
A lifting wavelet based lossless and lossy ECG compression processor for wireless sensors.
IEICE Electron. Express
Jiahui Luo, Zhijian Chen, Xiaoyan Xiang, Jianyi Meng
2017 — conf
A light-weight energy-efficient resilient circuit for variation tolerance.
ASICON
Xiaopei Chen, Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2017 J jnl
A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs.
IEICE Electron. Express
Sheng Wang, Chen Chen, Xiaoyan Xiang, Jianyi Meng
2017 — conf
A new error masking flip-flop with one cycle correction penalty.
ASICON
Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2017 J jnl
An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror.
IEEE Trans. Very Large Scale Integr. Syst.
Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2017 J jnl
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor.
IEICE Electron. Express
Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2016 J jnl
EDSU: Error detection and sampling unified flip-flop with ultra-low overhead.
IEICE Electron. Express
Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng, Yong Ding, Xiaolang Yan
2016 J jnl
Light-weight one-cycle timing error correction based on hardware software co-design.
IEICE Electron. Express
Li Zhanhui, Yong Ding, Xiaolang Yan, Jianyi Meng, Xiaoyan Xiang
2016 J jnl
TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor.
IEICE Electron. Express
Zhenqiang Yong, Xiaoyan Xiang, Jianyi Meng, Chen Chen
2016 J jnl
Ultralow power processor employing block instruction for ECG applications.
IEICE Electron. Express
Jing Qiu, Xiaoyan Xiang, Zhijian Chen, Jianyi Meng, Yong Ding
2016 J jnl
Value locality based storage compression memory architecture for ECG sensor node.
Sci. China Inf. Sci.
Chaojun Zhao, Chen Chen, Zhijian Chen, Jianyi Meng
2015 — conf
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction.
ASICON
Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2015 — conf
A timing failure tolerance design with in-field simultaneous error detection and correction.
ASICON
Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng
2015 — conf
An energy-efficient microprocessor using multilevel error correction for timing error tolerance.
ASICON
Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng