Jianwen Zhu - RankMe

64 papers A* 7A 16B 4C 3Misc 5Journal 12Unranked 17

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A unified intelligent control strategy synthesizing multi-constrained guidance and avoidance penetration. Sci. China Inf. Sci. Sibo Zhao, Jianwen Zhu, Weimin Bao, Xiaoping Li
2024	J	`jnl`	The Unconditional Consensus Control through Leadership for the Delayed Hegselmann-Krause Model. SIAM J. Control. Optim. Linglong Du, Jianwen Zhu, Feng Xie
2023	J	`jnl`	Multi-constrained intelligent gliding guidance via optimal control and DQN. Sci. China Inf. Sci. Jianwen Zhu, Hao Zhang, Sibo Zhao, Weimin Bao
2020	Misc	`conf`	Rotary Register File: A Micro-Architectural Primitive on FPGA. FCCM Reza Nakhjavani, Jianwen Zhu
2017	Misc	`conf`	A Case for Common-Case: On FPGA Acceleration of Erasure Coding. FCCM Reza Nakhjavani, Jianwen Zhu
2017	—	`conf`	A fast Bayesian algorithmic enhancement for real time bit error ratio test (BERT). GlobalSIP Shu-Yi Jack Wong, Jianwen Zhu
2016	B	`conf`	Write Amplification with Write Skew. MASCOTS Yue Yang, Jianwen Zhu
2016	J	`jnl`	Write Skew and Zipf Distribution: Evidence and Implications. ACM Trans. Storage Yue Yang, Jianwen Zhu
2015	J	`jnl`	A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks. IEEE Comput. Archit. Lett. Canwen Xiao, Yue Yang, Jianwen Zhu
2015	Misc	`conf`	Algebraic modeling of write amplification in hotness-aware SSD. SYSTOR Yue Yang, Jianwen Zhu
2014	Misc	`conf`	Analytical modeling of garbage collection algorithms in hotness-aware flash-based solid state drives. MSST Yue Yang, Jianwen Zhu
2012	A	`conf`	Saturating the transceiver bandwidth: switch fabric design on FPGAs. FPGA Zefu Dai, Jianwen Zhu
2011	Misc	`conf`	A bursty multi-port memory controller with quality-of-service guarantees. CODES+ISSS Zefu Dai, Jianwen Zhu
2011	—	`conf`	On virtual prototyping of embedded system-on-chips. ASICON Yi Ni, Wai Sum Mong, Jianwen Zhu
2011	—	`conf`	Register pressure aware scheduling for high level synthesis. ASP-DAC Rami Beidas, Wai Sum Mong, Jianwen Zhu
2011	A	`conf`	Regular fabric for regular FPGA (abstract only). FPGA Xun Chen, Jianwen Zhu
2011	B	`conf`	Timing-Driven Routing of High Fanout Nets. FPL Xun Chen, Jianwen Zhu, Minxuan Zhang
2011	J	`jnl`	Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu
2010	A	`conf`	A 1 cycle-per-byte XML parsing accelerator. FPGA Zefu Dai, Nick Ni, Jianwen Zhu
2010	A	`conf`	Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees. ICCAD Zefu Dai, Mark Jarvin, Jianwen Zhu
2010	—	`conf`	Interprocedural induction variable analysis based on interprocedural SSA form IR. PASTE Silvian Calman, Jianwen Zhu
2010	B	`conf`	Parallelizing Simulated Annealing-Based Placement Using GPGPU. FPL Alexander Choong, Rami Beidas, Jianwen Zhu
2010	A	`conf`	Towards scalable placement for FPGAs. FPGA Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu
2010	C	`conf`	Using variable clocking to reduce leakage in synchronous circuits. ICCD Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu
2009	B	`conf`	Increasing the Scope and Resolution of Interprocedural Static Single Assignment. SAS Silvian Calman, Jianwen Zhu
2009	A	`conf`	Towards automated ECOs in FPGAs. FPGA Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour
2009	C	`conf`	VariPipe: Low-overhead variable-clock synchronous pipelines. ICCD Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu
2008	—	`conf`	Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2008	J	`jnl`	Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2007	—	`conf`	BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2006	J	`jnl`	Dynamic-range estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bin Wu, Jianwen Zhu, Farid N. Najm
2005	A*	`conf`	A non-parametric approach for dynamic range estimation of nonlinear systems. DAC Bin Wu, Jianwen Zhu, Farid N. Najm
2005	—	`conf`	BDD-based two variable sharing extraction. ASP-DAC Dennis Wu, Jianwen Zhu
2005	J	`jnl`	Calligrapher: a new layout-migration engine for hard intellectual property libraries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianwen Zhu, Fang Fang, Qianying Tang
2005	J	`jnl`	Context sensitive symbolic pointer analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianwen Zhu, Silvian Calman
2005	—	`conf`	Scalable interprocedural register allocation for high level synthesis. ASP-DAC Rami Beidas, Jianwen Zhu
2005	A*	`conf`	Towards scalable flow and context sensitive pointer analysis. DAC Jianwen Zhu
2005	—	`conf`	Two-Dimensional Layout Migration by Soft Constraint Satisfaction. ISQED Qianying Tang, Jianwen Zhu
2004	—	`conf`	A queuing-theoretic performance model for context-flow system-on-chip platforms. ESTIMedia Rami Beidas, Jianwen Zhu
2004	A*	`conf`	An analytical approach for dynamic range estimation. DAC Bin Wu, Jianwen Zhu, Farid N. Najm
2004	—	`conf`	Automatic process migration of datapath hard IP libraries. ASP-DAC Fang Fang, Jianwen Zhu
2004	—	`conf`	Calligrapher: A New Layout Migration Engine Based on Geometric Closeness. ISQED Fang Fang, Jianwen Zhu
2004	A	`conf`	Dynamic range estimation for nonlinear systems. ICCAD Bin Wu, Jianwen Zhu, Farid N. Najm
2004	A	`conf`	DynamoSim: a trace-based dynamically compiled instruction set simulator. ICCAD Massimo Poncino, Jianwen Zhu
2004	—	`conf`	Piecewise quadratic waveform matching with successive chord iteration. ASP-DAC Zhong Wang, Jianwen Zhu
2004	—	`conf`	Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis. ISQED Khushwinder Jasrotia, Jianwen Zhu
2004	A*	`conf`	Symbolic pointer analysis revisited. PLDI Jianwen Zhu, Silvian Calman
2003	A*	`conf`	A retargetable micro-architecture simulator. DAC Wai Sum Mong, Jianwen Zhu
2003	A	`conf`	Performance Efficiency of Context-Flow System-on-Chip Platform. ICCAD Rami Beidas, Jianwen Zhu
2003	A	`conf`	Specification of Non-Functional Intellectual Property Components. DATE Jianwen Zhu, Wai Sum Mong
2003	A	`conf`	Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching. DATE Zhong Wang, Jianwen Zhu
2002	J	`jnl`	An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. Jianwen Zhu, Daniel D. Gajski
2002	C	`conf`	Hardware Implementation of a Memory Allocator. DSD Khushwinder Jasrotia, Jianwen Zhu
2002	A*	`conf`	Retargetable binary utilities. DAC Maghsoud Abbaspour, Jianwen Zhu
2002	A	`conf`	Symbolic pointer analysis. ICCAD Jianwen Zhu
2001	A	`conf`	Color Permutation: An Iterative Algorithm for Memory Packing. ICCAD Jianwen Zhu, Edward S. Rogers Sr.
2001	—	`conf`	Compiling SpecC for simulation. ASP-DAC Jianwen Zhu, Daniel Gajski
2001	A	`conf`	MetaRTL: raising the abstraction level of RTL design. DATE Jianwen Zhu
2001	A	`conf`	Static memory allocation by pointer analysis and coloring. DATE Jianwen Zhu
1999	—	`conf`	A unified formal model of ISA and FSMD. CODES Jianwen Zhu, Daniel Gajski
1999	A	`conf`	OpenJ: An Extensible System Level Design Language. DATE Jianwen Zhu, Daniel Gajski
1999	A*	`conf`	Soft Scheduling in High Level Synthesis. DAC Jianwen Zhu, Daniel Gajski
1998	—	`conf`	IP-Centric Methodology and Specification Language. DIPES Daniel Gajski, Rainer Dömer, Jianwen Zhu
1998	J	`jnl`	Specification and Design of Embedded Systems. Informationstechnik Tech. Inform. Rainer Dömer, Daniel D. Gajski, Jianwen Zhu