Jianwang Zhai

32 papers A* 5A 7C 2Journal 8Unranked 10
YearRankTypeTitle / Venue / Authors
2026 — conf
CHASE: A CHiplet Architecture Simulation and Exploration Framework with Decoupled Multi-Fidelity Optimization.
ISPD
Shixin Chen, Hengyuan Zhang, Jianwang Zhai, Bei Yu
2026 — conf
HLS-Timer: Fine-Grained Path-Level Timing Estimation for High-Level Synthesis.
ASP-DAC
Zibo Hu, Zhe Lin, Renjing Hou, Xingyu Qin, Jianwang Zhai, Kang Zhao
2026 — conf
Timing-Aware Optimization of Die-Level Routing and TDM Assignment for Multi-FPGA Systems.
ASP-DAC
Yijun Chen, Haoyuan Li, Chunyan Pei, Jianwang Zhai, Kang Zhao, Wenjian Yu
2025 — conf
AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design.
ACM Great Lakes Symposium on VLSI
Zichao Ling, Lin Li, Yi Huang, Yixin Xuan, Jianwang Zhai, Kang Zhao
2025 J jnl
DrlGoFPGA: FPGA Global Placement Considering Input-Output Buffer Based on Deep Reinforcement Learning and Gradient Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kang Yang, Jianwang Zhai, Liuyu Xiang, Zixi Huang, Dan Wu, Yida Wang, Kang Zhao, Ming Lei, Zhaofeng He
2025 J jnl
FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators.
CoRR
Shuao Jia, Zichao Ling, Chen Bai, Kang Zhao, Jianwang Zhai
2025 — conf
FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs.
ASP-DAC
Zirui Li, Kanglin Tian, Jianwang Zhai, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao
2025 A* conf
HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design.
DAC
Xinya Luan, Zhe Lin, Kai Shi, Jianwang Zhai, Kang Zhao
2025 C conf
HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules.
ISCAS
Zixuan Li, Kanglin Tian, Jianwang Zhai, Zirui Li, Kang Zhao
2025 A conf
IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning.
DATE
Feng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, Chuan Shi
2025 A* conf
IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction.
DAC
Feng Guo, Yueyue Xi, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Chuan Shi
2025 — conf
MILS: Modality Interaction Driven Learning for Logic Synthesis.
ACM Great Lakes Symposium on VLSI
Mingyu Zhao, Jiawei Liu, Jianwang Zhai, Chuan Shi
2025 — conf
PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis.
ASP-DAC
Guande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi, Kang Zhao
2025 — conf
The Survey of 2.5D Integrated Architecture: An EDA perspective.
ASP-DAC
Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu
2025 A conf
Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits.
ICCAD
Shan Shen, Shenglu Hua, Jiajun Zou, Jiawei Liu, Jianwang Zhai, Chuan Shi, Wenjian Yu
2025 J jnl
Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits.
CoRR
Shan Shen, Shenglu Hua, Jiajun Zou, Jiawei Liu, Jianwang Zhai, Chuan Shi, Wenjian Yu
2025 A* conf
Truly Pre-Routing Timing Prediction via Considering Power Delivery Network.
DAC
Yuyang Ye, Mingwei He, Lizheng Ren, Jianwang Zhai, Tinghuan Chen, Jun Yang, Longxing Shi
2025 A* conf
VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration.
DAC
Kai Shi, Zhe Lin, Xinya Luan, Jianwang Zhai, Kang Zhao
2025 A conf
WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction.
DATE
Jiawei Liu, Zhiyan Liu, Xun He, Jianwang Zhai, Zhengyuan Shi, Qiang Xu, Bei Yu, Chuan Shi
2024 J jnl
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration.
ACM Trans. Design Autom. Electr. Syst.
Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2024 C conf
Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing.
ISCAS
Zirui Li, Jianwang Zhai, Zixuan Li, Zhongdong Qi, Kang Zhao
2024 A conf
Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model.
DATE
Jingyu Jia, Jianwang Zhai, Kang Zhao
2024 — conf
PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing.
ACM Great Lakes Symposium on VLSI
Feng Guo, Jiawei Liu, Jianwang Zhai, Jingyu Jia, Kang Zhao, Chuan Shi
2024 A conf
PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network.
ICCAD
Jiawei Liu, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi
2024 J jnl
The Survey of Chiplet-based Integrated Architecture: An EDA perspective.
CoRR
Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu
2024 A* conf
Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.
AAAI
Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2023 J jnl
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
2023 J jnl
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning.
IEEE Trans. Very Large Scale Integr. Syst.
Jianwang Zhai, Yici Cai
2023 — conf
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning.
ASP-DAC
Jianwang Zhai, Yici Cai, Bei Yu
2021 A conf
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework.
ICCAD
Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
2021 A conf
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs.
ICCAD
Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
2021 J jnl
Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Jianwang Zhai, Yici Cai, Qiang Zhou