Jiann-Chyi Rau

27 papers A 3C 6Journal 3Unranked 15
YearRankTypeTitle / Venue / Authors
2024 — conf
A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism.
ISOCC
Jiann-Chyi Rau, Wei-Bin Yang, Yu-Lung Lo, Chin-Yuan Shih, Cheng-Kai Lin, Che-Chia Chuang
2021 — conf
A Scan-Based Lower-Power Testing Architecture for Modern Circuits.
ISPACS
Jiann-Chyi Rau, Jia-Xiang Wang
2013 J jnl
Compact Test Pattern Selection for Small Delay Defect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau
2012 — conf
Optimal unknown bit filtering for test response masking.
ISPACS
Ding-ke Weng, Jiann-Chyi Rau, Cheng-Han Lin
2011 J jnl
Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment.
IET Comput. Digit. Tech.
Jiann-Chyi Rau, Po-Han Wu
2010 C conf
Multi-chains encoding scheme in low-cost ATE.
ISCAS
Gong-Han Chen, Po-Han Wu, Jiann-Chyi Rau
2010 C conf
Multi-cycle compress technique for high-speed IP in low-cost environment.
ISCAS
Gong-Han Chen, Chu-Chuan Lin, Po-Han Wu, Jiann-Chyi Rau
2010 A conf
The AB-filling methodology for power-aware at-speed scan testing.
ITC
Tsung-Tang Chen, Po-Han Wu, Kung-Han Chen, Jiann-Chyi Rau, Shih-Ming Tzeng
2009 A conf
Low power multi-chains encoding scheme for SoC in low-cost environment.
ITC
Po-Han Wu, Jiann-Chyi Rau
2009 — conf
New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology.
Asian Test Symposium
Tsung-Tang Chen, Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau
2009 C conf
Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression.
ISCAS
Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau
2008 — conf
An efficient test-data compaction for low power VLSI testing.
EIT
Po-Han Wu, Tsung-Tang Chen, Wei-Lin Li, Jiann-Chyi Rau
2008 — conf
Test slice difference technique for low power encoding.
HLDVT
Wei-Lin Li, Tsung-Tang Chen, Po-Han Wu, Jiann-Chyi Rau
2008 — conf
The grid-based two-layer routing algorithm suitable for cell/IP-based circuit design.
ICECS
Chia-Jung Liu, Yi-Chen Lin, Jiann-Chyi Rau
2006 — conf
A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.
APCCAS
Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu
2006 C conf
A broadcast-based test scheme for reducing test size and application time.
ISCAS
Jiann-Chyi Rau, Jun-Yi Chang, Chien-Shiun Chen
2006 — conf
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs.
APCCAS
Jiann-Chyi Rau, Chien-Shiun Chen, Po-Han Wu
2005 — conf
A novel reseeding mechanism for pseudo-random testing of VLSI circuits.
ISCAS (3)
Jiann-Chyi Rau, Ying-Fu Ho, Po-Han Wu
2005 — conf
Reconfigurable multiple scan-chains for reducing test application time of SOCs.
ISCAS (6)
Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma
2004 — conf
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains.
Asian Test Symposium
Jiann-Chyi Rau, Ching-Hsiu Lin, Jun-Yi Chang
2003 — conf
An Efficient Mechanism for Debugging RTL Description.
IWSOC
Jiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin
2003 — conf
An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits.
IWSOC
Jiann-Chyi Rau, Kuo-Chun Kuo
2002 — conf
A don't-care based image circuit for function verification.
ISCAS (5)
Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang
2001 J jnl
A timing-driven pseudoexhaustive testing for VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shih-Chieh Chang, Jiann-Chyi Rau
2000 C conf
A compact factored form for a Boolean function.
ISCAS
Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang
2000 C conf
A timing-driven pseudo-exhaustive testing of VLSI circuits.
ISCAS
Shih-Chieh Chang, Jiann-Chyi Rau
1998 A conf
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
ITC
Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu