Jianlei Yang - RankMe

126 papers A* 14A 8C 7Journal 76Unranked 21

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu
2026	J	`jnl`	CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures. IEEE Trans. Computers Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2026	J	`jnl`	Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2026	J	`jnl`	Focus-dLLM: Accelerating Long-Context Diffusion LLM Inference via Confidence-Guided Context Focusing. CoRR Lingkun Long, Yushi Huang, Shihao Bai, Ruihao Gong, Jun Zhang, Ao Zhou, Jianlei Yang
2026	J	`jnl`	GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search. IEEE Trans. Computers Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2026	—	`conf`	MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator. ASP-DAC Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao May, Jianlei Yang
2026	A*	`conf`	SlimInfer: Accelerating Long-Context LLM Inference via Dynamic Token Pruning. AAAI Lingkun Long, Rubing Yang, Yushi Huang, Desheng Hui, Ao Zhou, Jianlei Yang
2025	J	`jnl`	ACE-GNN: Adaptive GNN Co-Inference with System-Aware Scheduling in Dynamic Edge Environments. CoRR Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu
2025	A*	`conf`	CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures. DAC Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao
2025	J	`jnl`	CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures. CoRR Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao
2025	J	`jnl`	CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures. CoRR Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2025	J	`jnl`	Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity. CoRR Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2025	A*	`conf`	Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design. ISCA Tianwei Pan, Tianao Dai, Jianlei Yang, Hongbin Jing, Yang Su, Zeyu Hao, Xiaotao Jia, Chunming Hu, Weisheng Zhao
2025	J	`jnl`	Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design. CoRR Tianwei Pan, Tianao Dai, Jianlei Yang, Hongbin Jing, Yang Su, Zeyu Hao, Xiaotao Jia, Chunming Hu, Weisheng Zhao
2025	J	`jnl`	GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search. CoRR Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2025	J	`jnl`	HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference. CoRR Cenlin Duan, Jianlei Yang, Rubing Yang, Yikun Wang, Yiou Wang, Lingkun Long, Yingjie Qi, Xiaolin He, Ao Zhou, Xueyan Wang, Weisheng Zhao
2025	J	`jnl`	MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator. CoRR Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao Ma, Jianlei Yang
2025	J	`jnl`	RELIC-GNN: Efficient State Registers Identification with Graph Neural Network for Reverse Engineering. CoRR Weitao Pan, Meng Dong, Zhiliang Qiu, Jianlei Yang, Zhixiong Di, Yiming Gao
2025	J	`jnl`	RLinf: Flexible and Efficient Large-scale Reinforcement Learning via Macro-to-Micro Flow Transformation. CoRR Chao Yu, Yuanqing Wang, Zhen Guo, Hao Lin, Si Xu, Hongzhi Zang, Quanlu Zhang, Yongji Wu, Chunyang Zhu, Junhao Hu, Zixiao Huang, Mingjie Wei, Yuqing Xie, Ke Yang, Bo Dai, Zhexuan Xu, Xiangyuan Wang, Xu Fu, Zhihao Liu, Kang Chen, Weilin Liu, Gang Liu, Boxun Li, Jianlei Yang, Zhi Yang, Guohao Dai, Yu Wang
2025	J	`jnl`	SlimInfer: Accelerating Long-Context LLM Inference via Dynamic Token Pruning. CoRR Lingkun Long, Rubing Yang, Yushi Huang, Desheng Hui, Ao Zhou, Jianlei Yang
2025	C	`conf`	Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms. ICCD Tong Qiao, Ao Zhou, Yingjie Qi, Yiou Wang, Han Wan, Jianlei Yang, Chunming Hu
2025	J	`jnl`	Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms. CoRR Tong Qiao, Ao Zhou, Yingjie Qi, Yiou Wang, Han Wan, Jianlei Yang, Chunming Hu
2025	A	`conf`	Ultra Energy-Efficient Butterfly Counting in Bipartite Networks via Algorithm-Architecture Co-Optimization. ICCAD Haiyang Liu, Xueyan Wang, Jianlei Yang, Xiaotao Jia, Gang Qu, Weisheng Zhao
2024	J	`jnl`	An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. IEEE Trans. Neural Networks Learn. Syst. Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao
2024	J	`jnl`	Architectural Implications of GNN Aggregation Programming Abstractions. IEEE Comput. Archit. Lett. Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu
2024	J	`jnl`	CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network. IEEE Trans. Emerg. Top. Comput. Huiyi Gu, Xiaotao Jia, Yuhao Liu, Jianlei Yang, Xueyan Wang, Youguang Zhang, Sorin Dan Cotofana, Weisheng Zhao
2024	J	`jnl`	DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2024	A*	`conf`	GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. DAC Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
2024	J	`jnl`	GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. CoRR Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
2024	A*	`conf`	Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. DAC Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2024	J	`jnl`	Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. CoRR Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2024	J	`jnl`	HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. CoRR Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
2024	J	`jnl`	HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. IEEE Trans. Computers Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
2024	—	`conf`	LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators. ITC-Asia Yicheng Huang, Xueyan Wang, Tianao Dai, Jianlei Yang, Zhaojun Lu, Xiaotao Jia, Gang Qu, Weisheng Zhao
2024	J	`jnl`	Pronunciation error detection model based on feature fusion. Speech Commun. Cuicui Zhu, Aishan Wumaier, Dongping Wei, Zhixing Fan, Jianlei Yang, Heng Yu, Zaokere Kadeer, Liejun Wang
2024	A*	`conf`	Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. DAC Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2024	J	`jnl`	Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. CoRR Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2024	A*	`conf`	WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA. DAC Mingjun Li, Pengjia Li, Shuo Yin, Shixin Chen, Beichen Li, Chong Tong, Jianlei Yang, Tinghuan Chen, Bei Yu
2023	J	`jnl`	Architectural Implications of GNN Aggregation Programming Abstractions. CoRR Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu
2023	J	`jnl`	DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory. CoRR Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2023	A*	`conf`	Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. DAC Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu
2023	J	`jnl`	Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. CoRR Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu
2023	J	`jnl`	IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao
2023	A*	`conf`	Lossy and Lossless (L ICCV Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang
2023	J	`jnl`	Lossy and Lossless (L CoRR Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang
2023	J	`jnl`	NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. Sci. China Inf. Sci. Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2023	J	`jnl`	TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices. CoRR Jianlei Yang, Jiacheng Liao, Fanding Lei, Meichen Liu, Junyi Chen, Lingkun Long, Han Wan, Bei Yu, Weisheng Zhao
2022	J	`jnl`	Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao
2022	J	`jnl`	Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform. CoRR Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2022	A*	`conf`	Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. DAC Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2022	—	`conf`	Exploring the Factors of Students' Online Learning Based On Structural Equation Modeling. TALE Han Wan, Hongzhen Luo, Zihao Zhong, Jianlei Yang
2022	J	`jnl`	NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration. CoRR Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2022	J	`jnl`	Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang
2022	J	`jnl`	S IEEE Trans. Computers Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao
2022	J	`jnl`	Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. CoRR Jianlei Yang, Xiaopeng Gao, Weisheng Zhao
2022	J	`jnl`	Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. IEEE Trans. Computers Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao
2021	A	`conf`	Brief Industry Paper: optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. RTAS Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu
2021	J	`jnl`	Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. IEEE Trans. Neural Networks Learn. Syst. Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
2021	J	`jnl`	Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoyi Wang, Shaobin Ma, Sheldon X.-D. Tan, Chase Cook, Liang Chen, Jianlei Yang, Wenjian Yu
2021	A	`conf`	FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. CIKM Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao
2021	J	`jnl`	FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. CoRR Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao
2021	J	`jnl`	Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. CoRR Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu
2021	J	`jnl`	RoSearch: Search for Robust Student Architectures When Distilling Pre-trained Language Models. CoRR Xin Guo, Jianlei Yang, Haoyi Zhou, Xucheng Ye, Jianxin Li
2021	J	`jnl`	S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. CoRR Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao
2021	J	`jnl`	Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. CoRR Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao
2020	J	`jnl`	A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao
2020	—	`conf`	Accelerating CNN Training by Pruning Activation Gradients. ECCV (25) Xucheng Ye, Pengcheng Dai, Junyu Luo, Xin Guo, Yingjie Qi, Jianlei Yang, Yiran Chen
2020	J	`jnl`	An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing. CCF Trans. High Perform. Comput. Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao
2020	J	`jnl`	Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. IEEE Trans. Circuits Syst. I Regul. Pap. Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang
2020	C	`conf`	Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method. ISCAS Chao Wang, Zhaohao Wang, Yansong Xu, Jianlei Yang, Youguang Zhang, Weisheng Zhao
2020	—	`conf`	Dual-Plane Switch Architecture for Time-Triggered Ethernet. ACM Great Lakes Symposium on VLSI Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang
2020	J	`jnl`	Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. CoRR Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
2020	J	`jnl`	Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques. CoRR Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
2020	J	`jnl`	Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques. ACM J. Emerg. Technol. Comput. Syst. Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
2020	J	`jnl`	Prototyping federated learning on edge computing systems. Frontiers Comput. Sci. Jianlei Yang, Yixiao Duan, Tong Qiao, Huanyu Zhou, Jingyuan Wang, Weisheng Zhao
2020	J	`jnl`	SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao
2020	A*	`conf`	SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. DAC Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao
2020	J	`jnl`	SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. CoRR Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao
2020	A*	`conf`	TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. DAC Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
2020	J	`jnl`	TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. CoRR Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
2020	A*	`conf`	TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework for Deep Learning with Anonymized Intermediate Representations. KDD Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang
2020	J	`jnl`	TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework with Anonymized Intermediate Representations. CoRR Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang
2020	—	`conf`	Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. ACM Great Lakes Symposium on VLSI Jianlei Yang, Xiaopeng Gao, Weisheng Zhao
2019	J	`jnl`	Accelerating CNN Training by Sparsifying Activation Gradients. CoRR Xucheng Ye, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
2019	J	`jnl`	ELFISH: Resource-Aware Federated Learning on Heterogeneous Edge Devices. CoRR Zirui Xu, Zhao Yang, Jinjun Xiong, Jianlei Yang, Xiang Chen
2019	—	`conf`	Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. ISVLSI Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao
2019	J	`jnl`	Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao
2019	C	`conf`	Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface. ISCAS Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Sai Li, Youguang Zhang, Weisheng Zhao
2019	J	`jnl`	Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. Sustain. Comput. Informatics Syst. Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang
2019	J	`jnl`	SPINBIS: Spintronics based Bayesian Inference System with Stochastic Computing. CoRR Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao
2019	C	`conf`	SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing. ISCAS Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Youguang Zhang, Weisheng Zhao
2019	A*	`conf`	eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. DAC Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao
2019	J	`jnl`	eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. CoRR Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao
2018	—	`conf`	A Novel Approach on Entity Linking for Encyclopedia Infoboxes. CCKS Xufeng Li, Jianlei Yang, Richong Zhang, Hongyuan Ma
2018	—	`conf`	A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. FPT Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
2018	J	`jnl`	A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. CoRR Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
2018	J	`jnl`	Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit Obfuscation. CoRR Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao
2018	J	`jnl`	Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. J. Comput. Sci. Technol. Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng
2018	—	`conf`	Spintronics based stochastic computing for efficient Bayesian inference system. ASP-DAC Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao
2017	—	`conf`	Generative adversarial network based scalable on-chip noise sensor placement. SoCC Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi
2017	—	`conf`	Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. TrustCom/BigDataSE/ICESS Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang
2017	C	`conf`	Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. ICCD Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang
2017	J	`jnl`	Spintronics based Stochastic Computing for Efficient Bayesian Inference System. CoRR Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Li, Weisheng Zhao
2017	A	`conf`	Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. ICCAD Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao
2016	—	`conf`	A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. ISVLSI Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li
2016	—	`conf`	A novel circuit design of true random number generator using magnetic tunnel junction. NANOARCH You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao
2016	J	`jnl`	Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. IEEE Trans. Very Large Scale Integr. Syst. Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao
2016	A	`conf`	ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. ICCAD Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie
2016	J	`jnl`	Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li
2016	—	`conf`	Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. ACM Great Lakes Symposium on VLSI Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu
2016	J	`jnl`	Spintronic Memristor as Interface Between DNA and Solid State Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li
2016	J	`jnl`	Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. IEEE Trans. Reliab. Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao
2015	—	`conf`	A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. ACM Great Lakes Symposium on VLSI Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia
2015	J	`jnl`	A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. IEEE Trans. Very Large Scale Integr. Syst. Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao
2015	C	`conf`	An overview on memristor crossabr based neuromorphic circuit and architecture. VLSI-SoC Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li
2015	—	`conf`	Early stage real-time SoC power estimation using RTL instrumentation. ASP-DAC Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai
2014	—	`conf`	Fast vectorless power grid verification using maximum voltage drop location estimation. ASP-DAC Wei Zhao, Yici Cai, Jianlei Yang
2014	J	`jnl`	Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi
2014	—	`conf`	Power supply noise aware evaluation framework for side channel attacks and countermeasures. FPT Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou
2014	J	`jnl`	PowerRush: An Efficient Simulator for Static Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
2013	—	`conf`	A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. ASP-DAC Wei Zhao, Yici Cai, Jianlei Yang
2013	C	`conf`	Selected inversion for vectorless power grid verification by exploiting locality. ICCD Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao
2012	A	`conf`	PowerRush : Efficient transient simulation for power grid analysis. ICCAD Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
2011	A	`conf`	Fast poisson solver preconditioned method for robust power grid analysis. ICCAD Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi
2011	—	`conf`	Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze
2011	A	`conf`	PowerRush: A linear simulator for power grid. ICCAD Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou