Jiangyuan Gu

19 papers A* 5A 1Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2026 — conf
2.9 A 0.24mJ/Frame Quadratic Interpolation 4DGS Processor with Recursive Computation Reuse and Tree-Based Parallel-Rendering.
ISSCC
Xiaolong Yang, Yang Wang, Wende Xu, Yubin Qin, Huanyu Wang, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu, Shouyi Yin
2026 — conf
A 28nm Speculative-Decoding LLM Processor Achieving 105-to-685µs/Token Latency for Billion-Parameter Models.
ISSCC
Yang Wang, Huanyu Wang, Jiaxin Yang, Yutong Su, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu, Shouyi Yin
2025 — conf
Computing Efficiency Improvement for Multi-PEA CGRA with Built-in Control Design.
CF
Jiangyuan Gu, Xunbo Hu, Zidi Qin, Shaojun Wei, Shouyi Yin
2025 — conf
DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures.
ASP-DAC
Haojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin
2025 A conf
P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture.
ICCAD
Qidie Wu, Jiangyuan Gu, Xuguang Yuan, Shaojun Wei, Shouyi Yin
2023 A* conf
RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA.
DAC
Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2023 J jnl
TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin
2023 J jnl
WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow.
CoRR
Haojia Hui, Jiangyuan Gu, Xunbo Hu, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2022 A* conf
GEML: GNN-based efficient mapping method for large loop applications on CGRA.
DAC
Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao
2022 A* conf
Mixed-granularity parallel coarse-grained reconfigurable architecture.
DAC
Jinyi Deng, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu, Boxiao Han, Fei Xu, Leibo Liu, Shaojun Wei, Shouyi Yin
2021 — conf
A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating.
ASP-DAC
Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
2021 — conf
Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs.
ASP-DAC
Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
2020 A* conf
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.
DAC
Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin
2018 J jnl
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.
IEEE J. Solid State Circuits
Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei
2018 J jnl
Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.
IEEE Trans. Parallel Distributed Syst.
Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
2017 J jnl
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory.
IEEE Trans. Parallel Distributed Syst.
Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei
2017 — conf
Energy-aware loops mapping on multi-vdd CGRAs without performance degradation.
ASP-DAC
Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
2017 A* conf
Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect.
DAC
Jiangyuan Gu, Shouyi Yin, Shaojun Wei
2016 J jnl
Joint Modulo Scheduling and V
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei