Jiangmin Gu

13 papers Journal 2Unranked 11
YearRankTypeTitle / Venue / Authors
2023 — conf
The Investigation of Source Field Plate on the Performance of pGaN Gate Device and Dual-Gate Bidirectional Switch using TCAD Simulation.
ICICDT
Xuan Chi, Yubo Wang, Fan Li, Yixiao Huang, Chenruiyuan Yu, Shiqiang Wu, Huiqing Wen, Jiangmin Gu, Ping Zhang, Wen Liu
2011 — conf
A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process.
ISOCC
Jinna Yan, Kok Meng Lim, Jiangmin Gu, Keping Wang, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo
2011 — conf
SiGe BiCMOS power amplifiers for 60GHz ISM band applications.
ISOCC
Renjing Pan, Jiangmin Gu, Kiat Seng Yeo, Wei Meng Lim, Kaixue Ma
2011 — conf
Ultra low power active 60 GHz Bi-CMOS down-conversion mixer.
ISOCC
Kok Meng Lim, Jiangmin Gu, Jinna Yan, Wei Meng Lim, Yang Lu, Kiat Seng Yeo
2010 — conf
Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving power.
ICECS
Kok Meng Lim, Jiangmin Gu, Yang Lu, Jinna Yan, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo
2005 — conf
A novel covalent redundant binary Booth encoder.
ISCAS (1)
Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy
2005 J jnl
A review of 0.18-μm full adder performances for tree structured arithmetic circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang
2005 — conf
An area efficient 64-bit square root carry-select adder for low power applications.
ISCAS (4)
Yajuan He, Chip-Hong Chang, Jiangmin Gu
2004 J jnl
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang
2003 — conf
A novel hybrid pass logic with static CMOS output drive full-adder cell.
ISCAS (5)
Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang
2003 — conf
Low voltage, low power (5: 2) compressor cell for fast arithmetic circuits.
ICASSP (2)
Jiangmin Gu, Chip-Hong Chang
2003 — conf
Ultra low voltage, low power 4-2 compressor for high speed multiplications.
ISCAS (5)
Jiangmin Gu, Chip-Hong Chang
2002 — conf
An interconnect optimized floorplanning of a scalar product macrocell.
ISCAS (1)
Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo