Jianglin Du - RankMe

12 papers Journal 8Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator. IEEE J. Solid State Circuits Teerachot Siriburanon, Xi Chen, Chunxiao Liu, Jianglin Du, Anding Zhu, Robert Bogdan Staszewski
2023	J	`jnl`	A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. IEEE J. Solid State Circuits Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
2022	J	`jnl`	A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. IEEE J. Solid State Circuits Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2022	J	`jnl`	A Compact 0.2-0.3-V Inverse-Class-F IEEE J. Solid State Circuits Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Enis Kobal, Philip Quinlan, Anding Zhu, Robert Bogdan Staszewski
2022	J	`jnl`	Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
2021	—	`conf`	A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. VLSI Circuits Jianglin Du, Teerachot Siriburanon, Xi Chen, Yizhe Hu, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2021	J	`jnl`	A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. IEEE J. Solid State Circuits Jianglin Du, Teerachot Siriburanon, Yizhe Hu, Vivek Govindaraj, Robert Bogdan Staszewski
2021	J	`jnl`	A Type-II Phase-Tracking Receiver. IEEE J. Solid State Circuits Suoping Hu, Jianglin Du, Peng Chen, Hieu Minh Nguyen, Philip Quinlan, Teerachot Siriburanon, Robert Bogdan Staszewski
2021	J	`jnl`	Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS. IEEE Open J. Circuits Syst. Ali Esmailiyan, Jianglin Du, Teerachot Siriburanon, Filippo Schembari, Robert Bogdan Staszewski
2020	—	`conf`	17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. ISSCC Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Zhong Gao, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2019	—	`conf`	A 0.3V, 35% Tuning-Range, 60kHz 1/f CICC Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019	—	`conf`	DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. APCCAS Vivek Govindaraj, Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski