Jiangli Huang - RankMe

11 papers A* 1C 1Journal 7Unranked 2

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Atelier: An Automated Analog Circuit Design Framework via Multiple Large Language Model-Based Agents. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinyi Shen, Zihao Chen, Ji Zhuang, Jiangli Huang, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng
2026	J	`jnl`	Variation-aware Analog Circuit Design via Contextual Modeling and Robust Optimization. ACM Trans. Design Autom. Electr. Syst. Jiangli Huang, Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2025	J	`jnl`	AnalogSeeker: An Open-source Foundation Language Model for Analog Circuit Design. CoRR Zihao Chen, Ji Zhuang, Jinyi Shen, Xiaoyue Ke, Xinyi Yang, Mingjie Zhou, Zhuoyao Du, Xu Yan, Zhouyang Wu, Zhenyu Xu, Jiangli Huang, Li Shang, Xuan Zeng, Fan Yang
2025	J	`jnl`	HSG-RAG: Hierarchical Knowledge Base Construction for Embedded System Development. ACM Trans. Design Autom. Electr. Syst. Zhouyang Lu, Hailin Xu, Anrui Chen, Siyuan Tang, Junyi Zhang, Yifei Feng, Wentao Pan, Jiangli Huang
2024	J	`jnl`	A Compact 0.1-1.95 GHz, 1.5 dB NF LNTA Based on Cascode Inverters. IEEE Trans. Circuits Syst. II Express Briefs Cong Tao, Jiangli Huang, Liangbo Lei, Yumei Huang, Zhiliang Hong, Xiaoyang Zeng
2024	A*	`conf`	Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. DAC Zihao Chen, Jiangli Huang, Yiting Liu, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng
2023	J	`jnl`	An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling. IEEE Trans. Circuits Syst. I Regul. Pap. Jiangli Huang, Chuyu Wang, Yuyang Yan, Cong Tao, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
2023	J	`jnl`	Automatic Op-Amp Generation From Specification to Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jialin Lu, Liangbo Lei, Jiangli Huang, Fan Yang, Li Shang, Xuan Zeng
2021	—	`conf`	A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. ASP-DAC Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021	C	`conf`	Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. ISCAS Jiangli Huang, Shuhan Zhang, Cong Tao, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2021	—	`conf`	New Linearization Implementations Improving IIP3 of Wideband LNTA by More than 14dB. ASICON Cong Tao, Liangbo Lei, Jiangli Huang, Zhipeng Chen, Yumei Huang, Zhiliang Hong