Jiangchao Wu - RankMe

12 papers C 2Journal 5Unranked 5

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A 0.013 mm² 3.2-ns Input Range 10-Bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Xin Lu, Jiangchao Wu, Zhao Wang, Yifei Xiang, Liyuan Liu, Pui-In Mak, Rui Paulo Martins, Man-Kay Law
2024	—	`conf`	A 0.25pJ/Comparison, 27.3μV Input Noise Dynamic Comparator Exploiting Stacked Floating Preamplifier with Cross-Coupled Feedback Inverters in 180nm CMOS. CICC Jiangchao Wu, Ke Hu, Xuanlin Chen, Pui-In Mak, Rui Paulo Martins, Man Kay Law
2024	—	`conf`	A 0.9V CMOS Voltage Reference with 0.41% Untrimmed Accuracy and 44.7 ppm/°C TC from -35°C to 130°C. A-SSCC Xuanlin Chen, Jiangchao Wu, Bo Wang, Man Kay Law
2024	—	`conf`	A 33.6nW Capacitively Coupled Chopper Amplifier with Stacked Input-Boosted Gate-and-Bulk-Driven Inverter Achieving 0.59 NEF and 0.42 PEF in 180nm CMOS. A-SSCC Ke Hu, Jiangchao Wu, Bo Wang, Man Kay Law
2024	J	`jnl`	A 93.4% Peak Efficiency C IEEE J. Solid State Circuits Feiyu Li, Qishen Fang, Jiangchao Wu, Yang Jiang, Pui-In Mak, Rui Paulo Martins, Man-Kay Law
2023	—	`conf`	Fully Integrated Reconfigurable Solar Energy Harvester for $100\mu\mathrm{A}$ Burst Output Current Delivery with 78.6% Peak Energy Extraction Efficiency and Minimum Startup Incident Light Power of 0.27mW/cm A-SSCC Jiangchao Wu, Guangshu Zhao, Litao Zhang, Yu Jia, Yang Jiang, Pui-In Mak, Rui Paulo Martins, Man Kay Law
2022	—	`conf`	High Linearity BJT-Based Time-Domain CMOS Temperature Sensor. APCCAS Yu Lei, Qishen Fang, Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins
2021	J	`jnl`	A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Jiangchao Wu, Hou-Man Leong, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo Martins
2020	C	`conf`	Low Complexity Illumination-Invariant Motion Vector Detection Based on Logarithmic Edge Detection and Edge Difference. ISCAS Chuanqi Wei, Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Jiangchao Wu, Ka-Chon Lei, Hou-Man Leong, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo Martins
2016	J	`jnl`	A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop. IEEE Trans. Circuits Syst. II Express Briefs Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins
2013	C	`conf`	A 1.83 μW, 0.78 μVrms input referred noise neural recording front end. ISCAS Jiangchao Wu, Man-Kay Law, Pui-In Mak, Rui Paulo Martins